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Method and Apparatus for Controlling the TSV Structure Characteristics in 3D Stack

IP.com Disclosure Number: IPCOM000238441D
Publication Date: 2014-Aug-26
Document File: 2 page(s) / 34K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for controlling the TSV structure characteristics in 3D stack.

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This is the abbreviated version, containing approximately 100% of the total text.

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Method and Apparatus for Controlling the TSV Structure Characteristics in 3

33D Stack

D Stack

Through Silicon Via (TSV) based designs are emerging and generally used for conducting the power and signal lines traversing across the stack in combination with micro bumps. The TSVs are effective signal conductors in 3D chip stack, especially stacked chips with regulator in built and generally used separately, and the invention proposes to design a technique to use them in combination based on the critical path timing requirement. Dynamically choosing a TSV farm comprising of optimized number of TSVs in parallel can improve the overall performance at the cost of increased redundancy. The low frequency and high current signals are routed through the TSV farms with highest number of TSVs in parallel (minimum resistance) for reduced I^2R power dissipation. On the other hand, high frequency signals with low current levels are routed through the TSV farms with lowest number of TSVs in parallel (minimum capacitance), thereby increasing the speed of communication. This architecture is especially attractive with integrated voltage regulator modules providing varying voltage/currents for peak performance (see the figure below).

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