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Standard Cell Layout Scheme with Improved Rail Capacitance

IP.com Disclosure Number: IPCOM000238466D
Publication Date: 2014-Aug-27
Document File: 4 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

As technology shrinks, more and more logic is being implemented in a system on a chip (SOC). This has resulted in a surge in current demand. Hence there is need to have more and more decoupling capacitors (decaps) in the chip. More on-die decap implementation would increase overhead and cost. Hence, there is a strong need to increase the effectiveness of the ‘used-up’ resources on the die to reduce the cost overhead without impacting the design parameters. This paper presents a standard cell layout scheme with improved rail capacitance.

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Standard Cell Layout Scheme with Improved Rail Capacitance

Abstract

As technology shrinks, more and more logic is being implemented in a system on a chip (SOC).  This has resulted in a surge in current demand. Hence there is need to have more and more decoupling capacitors (decaps) in the chip. More on-die decap implementation would increase overhead and cost. Hence, there is a strong need to increase the effectiveness of the ‘used-up’ resources on the die to reduce the cost overhead without impacting the design parameters. This paper presents a standard cell layout scheme with improved rail capacitance.

Problem Definition

Meeting the IR Drop requirement is becoming more and more difficult with increasing design speed and complexity. Sufficient area has to be reserved for decap addition to take care of this requirement. This decap which is added in later stages of design is not available uniformly. So the challenge is to increase the decap in the chip without impacting chip area. Hence the need is to optimize the standard cells for better inbuilt decap.

 

Proposed Solution

We propose the following standard cell layout to increase the power rail capacitance without hampering the area and timing:

•      Shift VDD/VSS rails of M1 and M2 of standard cells inside the PR Boundary of standard cell. Now there is dedicated M1 and M2 power rail for each cell (no sharing).

•      Reduce the width of M2 rail to same as the width of M1 rail as there would not be the power rail sharing by tw...