Browse Prior Art Database

Graphene Interconnect Structure and Formation

IP.com Disclosure Number: IPCOM000238470D
Publication Date: 2014-Aug-27
Document File: 3 page(s) / 54K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a multi-level interconnect system that comprises Graphene to improve the conductivity of circuit wiring and electrical reliability. The integration method is compatible with wafer-level Complementary Metal Oxide Semiconductor (CMOS) fabrication.

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Graphene Interconnect Structure and Formation

With the aggressive device scaling, Cu resistivity is greatly affected by smaller geometry at a nano scale due to electron surface scattering and grain-boundary scattering. Wiring resistance goes higher, leading to increased RC delay.

One possible solution is to replace copper with silver; however, the silver metallization is difficult and silver is less conductive than Graphene.

The novel solution is a multi-level interconnect system that comprises Graphene to improve the conductivity of circuit wiring and electrical reliability. The integration method is compatible with wafer-level Complementary Metal Oxide Semiconductor (CMOS) fabrication. With this system, the trench metal consists of Cu and Graphene. Cu is the catalyst for forming super conductive Graphene. The approach uses single damascene via processing and subtractive trench etch processing.

Figure 1: Proposed Structure

Figures 2-7 represent the steps for the integration flow in a preferred embodiment.

Figure 2: Step 1. Deposit M2 low-k, pattern to define V1. V1 etch stops at Cu/Graphene interface.

Figure 3: Step 2. Deposit Ta/TaN then fill in with Cu plating; Chemical Mechanical Planarization (CMP) polish until barrier endpoint.

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Figure 4: Step 3. Physical Vapor Deposit (PVD) Cu seed layer 1~2nm.

Figure 5: Step 4. Low-T Chemical Vapor Deposition (CVD) growth of Graphene layer 1~10A.

Figure 6: Step 5. Etch unwanted M2 Cu/Graphene metal areas.

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