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Flexible Interface Timing for JESD207 Based Antenna Interface

IP.com Disclosure Number: IPCOM000238518D
Publication Date: 2014-Sep-02
Document File: 5 page(s) / 170K

Publishing Venue

The IP.com Prior Art Database

Abstract

Small cell baseband System on Chip (SoC) has an antenna interface integrated on chip to interface with Radio Frequency (RF) transceiver (RFIC). This interface is standardized and called JESD207 interface. The protocol specifies the handshaking signals between baseband and RFIC. JESD207 specified timing requirements from RFIC state change to valid data. These timing requirements may not be met by all RFIC implementations and may vary for same RFIC in different configurations.

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Flexible Interface Timing for JESD207 Based Antenna Interface

Abstract

Small cell baseband System on Chip (SoC) has an antenna interface integrated on chip to interface with Radio Frequency (RF) transceiver (RFIC). This interface is standardized and called JESD207 interface. The protocol specifies the handshaking signals between baseband and RFIC.  JESD207 specified timing requirements from RFIC state change to valid data. These timing requirements may not be met by all RFIC implementations and may vary for same RFIC in different configurations.

Introduction

The interface timing is driven by the timers running on baseband. The interface between baseband and RFIC can implement LTE-TDD and LTE-FDD protocol. In FDD (Frequency Division Duplex) the data of transmit (Tx) and Receive (Rx) stream is modulated on different frequency spectrum to enable the duplex communication. It makes mandatory for RFIC/Power Amplifier (PA) always ON for Tx and Rx.

In TDD (Time Division Duplex) the data of Tx and Rx are time multiplexed on same frequency spectrum. It makes mandatory to switch ON and OFF Tx and Rx processing chain in RFIC as well respective PA based on direction of stream.

JESD207 Specifies that for a transmit burst, the time from Enable pulse to valid data shall be 2 clocks. Similarly, for a receive burst, the time from Enable pulse to valid data shall be 2 clocks.

Typically, the transmit burst will be enabled as soon as the receive burst has ended in order to provide RFIC time to power up its Digital to Analog Converters (DAC), Oscillators and Filters. So, the RFIC may not be able to accept data as 2 clocks after Enable pulse. Additionally, as the baseband has enabled the transmit burst early, it may not have valid data to transmit within 2 clocks. To allow RFIC and Baseband to communicate validity of transmit data, this solution adds a signal “TX_DATA_VALID” to JESD207 interface. This signal is asserted by baseband when valid data is presented on the interface. When this signal is not asserted, the RFIC will treat data from baseband as “zeros”.

The receive burst will also be enabled as soon as transmit burst has ended so that RFIC and PA components can be powered up early and valid data can be provided to the baseband for the TDD receive cycle. The JESD207 requirement of 2 clocks from Enable to valid data may not also be met in receive cycle by RFIC. To allow RFIC to send valid data at any time after receive burst has been enabled, the solution is to add “RX_DATA_VALID” signal to RFIC Baseband interface. RFIC will assert this signal when it has valid data to send to the baseband. When RX_DATA_VALID signal is de-asserted, the baseband...