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A Method for Fabricating a Silicon On Insulator (SOI) Substrate with Two Types of Strain

IP.com Disclosure Number: IPCOM000238624D
Publication Date: 2014-Sep-08
Document File: 5 page(s) / 88K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for fabricating a Silicon On Insulator (SOI) substrate with two types of strain.

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This is the abbreviated version, containing approximately 53% of the total text.

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A Method for Fabricating a Silicon On Insulator ( Strain


Disclosed is a method for fabricating a Silicon On Insulator (SOI) substrate with two types of strain.

The method and system utilizes direct wafer bonding to form a strained Silicon (Si) layer on a relaxed Si layer on the SOI substrate. For a p-Field Effect Transistor (PFET), the strained Si layer and a dislocation layer are etched away and compressive strained Silicon Germanium (SiGe) is grown on top of the relaxed Si layer. Thereafter, a thermal mixing (condensation method) is performed for one of the Si layer and the SiGe after

which only strained SiGe remains forming a structure with two types of strain .

Fig. 1 illustrates the first step of fabricating the two types of strained regions on the SOI substrate.

Figure 1

As shown in fig. 1, the strained Si layer (a donor wafer) is grown on a relaxed SiGe virtual substrate. In an exemplary scenario, a Graded SiGe Layer (GBL) is grown on a Si layer to reach the desired Germanium (Ge) concentration, and then the strained Si layer is grown.

Fig. 2 illustrates the step of bonding sSOI structure on top of a handle wafer .

) ((SOI

SOI)

Substrate with Two Types of

Substrate with Two Types of

1


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Figure 2

Fig. 3 illustrates the next step of removing the donor wafer and the SiGe by one of grinding, etching back, smart cutting or utilizing a combination of these.

Figure 3

Fig. 4 illustrates the subsequent step of defining regions within the substrate where high performances n-Field Effect Transistors (NFETs) are required to be fabricated.

2


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Figure 4

The regions are also defined for etching away the strained Si layer and defective layers from the rest of the wafer.

Thereafter, a step of forming a Shallow...