Browse Prior Art Database

Dual channel CMOS with comparable electrostatics

IP.com Disclosure Number: IPCOM000238626D
Publication Date: 2014-Sep-08
Document File: 4 page(s) / 94K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a method and structure for forming a dual channel Complimentary Metal-Oxide Semiconductor (CMOS) with comparable electrostatics.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 78% of the total text.

Page 01 of 4

Dual channel CMOS with comparable electrostatics

Different channel materials are needed for future Complimentary Metal -Oxide Semiconductor (CMOS) scaling (e.g., Silicon (Si) or III-V for negative Field Effect Transistor (nFET) and Germanium (Ge) for positive Field Effect Transistor (pFET)). Different channel materials have different permittivity (e.g., Si is ~11.9 and Ge is ~16). For highly scaled Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) with short Lgate, the electrostatics is a strong function of the permittivity of channel materials. Therefore, there is a need to achieve dual channel CMOS with comparable electrostatics.

The novel solution provides a method and structure for forming a dual channel CMOS

with comparable electrostatics. One FET has dual spacers and the others have a single spacer.

The process flow is illustrated in the following figures.

Figure 1:

1. Start with dual channels (e.g., Si for nFET and Ge or SiGe for pFET) on a substrate; channel can be planar, fin, nanowire, etc.


2. Form isolation (e.g., Shallow Trench Isolation (STI) or mesa)


3. Form dummy gate

Figure 2:


4. Form dual spacers (e.g., oxide spacer + nitride spacer)


5. Form source/drain epitaxy (epi) for nFET and pFET

1


Page 02 of 4

Figure 3:

6. Deposit Inter-Layer Dialectric (ILD) oxide and Chemical-Mechanical Planarization (CMP)

Figure 4:


7. Mask nFET and remove dummy gate from pFET

Figure 5:


8. Remove oxide spacer from pFET, nitride spacer remains

2


Page 03 of 4

Fig...