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Method to Reduce Leakage Power by Balancing Threshold Voltage

IP.com Disclosure Number: IPCOM000238640D
Publication Date: 2014-Sep-09
Document File: 3 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to reduce leakage power by balancing threshold voltage along a path. Leakage power is typically reduced by raising the threshold voltage of a single gate. This method looks at an entire path and changes the threshold voltage of multiple gates, moves latches, and skews clocks in order to minimize the leakage voltage, while maintaining the slack goal.

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Method to Reduce Leakage Power by Balancing Threshold Voltage

When automated tools are used to place cells in a microprocessor or ASIC design, there are many factors that influence where the cells are placed, such as logical connections and timing. Power is not typically a factor, and even if you were able to meet your frequency target, it does not mean that you found the lowest power solution. This invention shows a method to reduce the leakage power by balancing the threshold voltage of cells on the input and output of a latch.

    There are existing techniques to move latches to improve negative slack times, but not aware of any existing solution other than manual analysis to move latches to optimize power. It is not uncommon to see a long path with a long buffer chain of low threshold voltage (vt) with a lot of leakage current on the input of a latch. While the output of the latch has a short distance to travel to the next sink, so it contains very few high vt cells with very little leakage current. This idea would notice the difference in leakage current between the latch input and output and move the latch to balance the leakage current.

    In Figure 1 below, latch A is placed 400 design units away from latch B. Latch B is placed adjacent to latch C. The path from latch A to latch B was difficult to close timing, and four buffers with high power were added to satisfy the setup test requirement at latch B. The setup slack at latch C is significantly positive. The high power buffers have a delay of 100 units and power of 400 units. Total power is 4 x 400 = 1600 units. The timing calculations are:

        A output B input B output C input arrival time 0 400 0 0 required time 0 400 400 400 slack

Figure 1

    
By utilizing some of the positive slack between latches B and C, one can safely move latch B closer to the source latch A (see Figure 2 below). By doing this, the distance between latch A and B is shorter and now only requires two low power buffers. Since latch B was moved further from C, one now needs two new low power buffers to maintain positive late mode slack. Low power buffers have a delay of 150 units and power of 100 units. Total power is now 4x100 = 400 units. The new timing calculations are:

A output B input B output C input

0 0 400 400

1


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arrival time 0 300 0 300 required time 0 300 0 300 slack

Figure 2

    
The net area between these two diagrams is equal and both had positive late mode slack, but the leakage power is significantly less in Figure 2. The flowchart for this invention is as follows:
100) Get a list of latches to check
110) If there are latches that haven't been checked yet, get a latch from the list. Else, go to 400. 200) Trace back the data input to the latch. Are there buffers on the input of the latch? If no, go to 300.
210) Are any of the input buffers candidates for power reduction? If no, go to 300 (candidates are buffers which have not already lowest power and have not already been evaluated).
220) Pick one...