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Multi-bit Level Shifter Isolation Cell

IP.com Disclosure Number: IPCOM000238775D
Publication Date: 2014-Sep-17
Document File: 5 page(s) / 145K

Publishing Venue

The IP.com Prior Art Database

Abstract

Chip size and routing congestion issues are always a big challenge for SoC (System on Chip) designers. There are many level shifter and isolation cells in low power designs that occupy extra area and routing tracks. A level shifter isolation cell is the combination of a level shifter cell and an isolation cell. In this paper, a multi-bit level shifter isolation cell is proposed to merge separated level shifter isolation cells together. In this way, common logic in level shifter isolation cells can be shared and merged, and the total number of cell pins on chip top can be reduced. This helps save chip area and reduce routing congestion.

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Multi-bit Level Shifter Isolation Cell

Abstract

Chip size and routing congestion issues are always a big challenge for SoC (System on Chip) designers. There are many level shifter and isolation cells in low power designs that occupy extra area and routing tracks.  A level shifter isolation cell is the combination of a level shifter cell and an isolation cell.  In this paper, a multi-bit level shifter isolation cell is proposed to merge separated level shifter isolation cells together.  In this way, common logic in level shifter isolation cells can be shared and merged, and the total number of cell pins on chip top can be reduced.  This helps save chip area and reduce routing congestion.

Introduction

As more and more devices are integrated into one chip, chip area and routing congestion are becoming more critical. On the other hand, low power design is another trend for many chips, especially for portable applications. There are many level-shifter and isolation cells in low power design, which are for MSV (Multi Support Voltage) and PSO (Power Shut Off) low power implementation. Level-shifter-isolation cell combines the function of level shifter cell and isolation cell. As usage of level-shifter-isolation cells is similar, and they usually centralize together between power domains, there is a chance to combine them together to save area and routing resource. The combined level-shifter-isolation cell is named as multi-bit level-shifter-isolation cell.

Design and Implementation

Level shifter and isolation cells are widely used in low power design. Level shifter cell is used to convert signals between different voltages for MSV design, and isolation cell is used to tie signals between power on domain and power off domain to avoid floating nodes in PSO design.

Figure 1 shows cell view of multi-bit level-shifter-isolation cell. Four separated level-shifter-isolation cells are merged into one 4-bit level-shifter-isolation cell. By combining level-shifter-isolation cells, common function pin “iso” (which is to determine state in isolation mode) could be merged; common power pins “vddhi”, ”vddlo”, ”wellb” could be merged; and common ground pins “vss”, “vssb” could be merged. These merged pins reduce total pin number at t...