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Multi-stack chip-to-wafer oxide bonding

IP.com Disclosure Number: IPCOM000238817D
Publication Date: 2014-Sep-19
Document File: 3 page(s) / 70K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is method for using oxide bonding in a chip-wafer bonding scheme that can enable wafer scale processing for subsequent bonding.

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This is the abbreviated version, containing approximately 76% of the total text.

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Multi-stack chip-to-wafer oxide bonding

Current wafer-to-wafer three-dimensional (3D) integration using oxide bonding has multiple disadvantages. It is extremely challenging to achieve ultra-high (<+/-0.5) wafer/chip alignment accuracy due to wafer expansion. There is chip loss due to a lack of control of know-good-die (KGD) stacking. Stack loss is experienced during the grinding of stacked wafers.

The novel solution to these problems is a process/integration method that takes advantages of wafer-level fabrication (fab) processing, ultra-high alignment accuracy resulting from chip-to-chip/wafer RT oxide bonding, and pre-stacking KGD diagnosis. The unique advantage and novelty of the solution is in the method to realize the wafer-level processing of chip-to-wafer oxide bonding for multi-stacking when chip sizes between wafers are different.

Following are the steps for the method for using oxide bonding in a chip-wafer bonding scheme that can enable wafer scale processing for subsequent bonding.

Figure 1: Preparation of chips from device wafer 1 (top)

Figure 2: Preparation of chips from device wafer 2 (bottom)

1


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Figure 3: Can first be further thinned to final Silicon (Si) thickness by selective Si Reactive Ion Etching (RIE)/wets

Gap 5-60 um


 Chip-wafer alignment accuracy: <1 um


 Dicing saw position accuracy: (5-10 um)

 Leaving 5-50 um of working space for bonding

Chip-grid height difference <2 um


 Wafer-to-wafer thickness variation as a re...