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Method for Restoring Field-Program Gate Array (FPGA) Configuration Bits Lost due to Single Event Upset

IP.com Disclosure Number: IPCOM000238830D
Publication Date: 2014-Sep-19
Document File: 1 page(s) / 35K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for restoring Field-Programmable Gate Array (FPGA) configuration bits lost due to single event upset.

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Method for Restoring Field-Program Gate Array (FPGA) Configuration Bits Lost due to Single Event Upset

Single event effects result in Field-Programmable Gate Array (FPGA) configuration bits getting corrupted over time. This may lead to improper functioning of the FPGA. FPGAs use Single Event Upset (SEU) detection logic to detect a configuration bit corruption. However, this logic has proven to be unreliable. SEU events accumulate at an average rate as time passes. Thus, the number of corruption events and the probability of configuration bit corruption causing an FPGA to function improperly increases with up-time since the previous FPGA configuration.

Disclosed is a method for restoring FPGA configuration bits lost due to SEU. The method restores the corrupted configuration bits by reconfiguring the FPGA. In particular, the method reconfigures the FPGA after up-time exceeds a predetermined value. The method utilizes an associated NOR flash for reconfiguring the FPGA. Limiting the time between FPGA configurations significantly reduces the probability of accumulated SEU events causing the FPGA to function improperly.

This method effectively refreshes the FPGA configuration at a constant time interval. The time interval is determined by the estimated SEU rate of the FPGA and what is deemed an acceptable accumulation of configuration bit errors due to SEU. The interval may also be varied so that the FPGA gets reconfigured at a minimally disruptive time for an interr...