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Efficient state retention flip flop for power savings with reduced area and power overhead

IP.com Disclosure Number: IPCOM000238869D
Publication Date: 2014-Sep-23
Document File: 4 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a new architecture on state retention flip-flops with several advantage over prior arts in the field of power (switching/active/leakage) and silicon area. Existing solutions retain the design state during sleep mode and provide power savings at the cost of considerable area and power overhead. This solution provides greater power savings and also reduces the area/power overhead necessary for state retention.

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Efficient state retention flip flop for power savings with reduced area and power overhead

    As we scale down to deep sub-micron technologies, leakage/active/switching currents are on a increasing trend, resulting in larger chip power dissipation. Power gating is an essential

power saving technique to cut down active and leakage power during chip idle modes. To minimize wake up time from chip idle modes, design state before entry into idle modes need to be retained. This results in a need for state retention flip-flop (SRPGFF) designs. Existing solutions retain the design state during sleep mode and provide power savings at the cost of considerable area and power overhead. This solution provides greater power savings and also reduces the area/power overhead necessary for state retention.

Conventional State retention flip flop design:

Figure 1

The conventional SRPGFF, as shown in Figure 1, uses a balloon/shadow latch to retain state.

The shadow latch is powered by always on power supply or Vretention supply(Vret).

When the chip is powered down by turning off the switched power supply, Vdd, the shadow latch will retain state since Vret remains on.

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This design results in a overhead of approximately 14 transistors.

Proposed State retention flip flop design:

Figure 2

In the proposed state retention flip-flop design, shown in Figure 2, the master latch is

powered by the switch power supply (Vdd) and the slave latch is powered by the always on

power supply (Vret).

A high-VT(threshold voltage) weak PMOS(Metal Oxide Semiconductor) pull-up transistor enabled by the retention enable signal (Ret_en) is added. Optionally, an NMOS pull-down transistor can also be used instead of the PMOS, as shown in dotted lines above in Figure 2.

A weak NMOS pull-down transistor enabled by the retention enabled signal is added on the CLK pin. This ensures that clock is driven to a clean 0 during sleep mode when retention enable is active. This pull-down is necessary if the chip clock distribution network is driven by the switch power supply, Vdd.

Alternatively, the clock distribution network can be driven by the always on power supply, Vret. In this scenario, the weak NMOS pull-down transistor is not necessary.

In the proposed solution, the transmission gate and inverter transistors in the forward path of the slave latch can be chosen to contain low threshold voltage devices whereas the feedback inverters can comprise of high threshold voltage devices. The PMOS pull up or NMOS pull down transistor is also chosen to be a high threshold device. The master latch transistors can be

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chosen to be high threshold voltage devices. The slave latch comprised of low threshold voltage devices helps improve performance of the flip-flop whereas the high threshold transistors in the feedback path and the master latch help to reduce the leakage power consumed by the flip-flop. In the proposed...