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Structure for redundant MISR comparison and improved LBIST testability

IP.com Disclosure Number: IPCOM000238882D
Publication Date: 2014-Sep-23
Document File: 5 page(s) / 414K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a solution to minimize the volume of data that must flow in and out of a computer chip that is being tested by taking advantage of repeating macros inside of chips and comparing the output of each macro to each other on the chip.

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Structure for redundant MISR comparison and improved LBIST testability

When testing computer chips, the volume of data that must flow in and out of a chip costs time and money. The solution to minimize this is to take advantage of repeating macros inside of chips and compare the output of each macro to each other on the chip. When there is a mismatch, this will signify a fault and the chip is bad. This method eliminates the need to transmit the expected value or the actual value for comparison to determine if the chip is functional or not. It also eliminates the problem of errors in simulation of test pattern outputs.

    The architectural changes are being shown with a central compare complex that can really be thought of as a series of such blocks depending upon what common elements exist within any given design. For example, in the system on a chip shown in Figure 1, such a complex would exist on the CPU side (left) to provide the functionality described for the three cores. In addition, there would likely be one within the L2 unit as it is constructed with a substantial amount of symmetry. Another would exist in Styx to service the identical left and right side units. There would also be such units within the GPU (right side of the SoC) that compare either all eight SP units (or the four top together uniquely from the four bottom together). The MC units would also have a structure associated with them, as would elements of the GDDR units (within the units and/or bottom unit to right side unit). Some of the large tiles, like the TCM, SX, etc., may also have sufficient symmetry internally to justify smaller such structures internal to each unit. With the addition of this functionality, a vast majority of the design can be covered with checks that essentially provide an internal consistency check for at speed LBIST patterns.

         As long as patterns are valid, on a cycle-by-cycle basis, as well as from LBIST pattern to LBIST pattern, any discrepancy can be immediately captured. Normal LBIST patterns are not able to be analyzed until a particular test is run to completion and compared against a final expected result. Much greater fail debug capability would exist as the very cycle of the fail can now be isolated. Trace array capability can be added to capture the stream of MISR data an...