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Cost effective programmable solution for generation of SAR-ADC controls

IP.com Disclosure Number: IPCOM000238904D
Publication Date: 2014-Sep-24

Publishing Venue

The IP.com Prior Art Database

Abstract

Analog to Digital Convertor (ADC) working in successive Approximation Register (SAR) method has mainly two phases for each conversion. Sample and evaluation phase. Comparator works in evaluation phase. Comparator has multiple stages. The On and off period of different stages of comparator in evaluation phase plays important role to define the quality of ADC output. In general the on and off duration of each phase is defined by particular values of a specified set of control signals. The control signals are driven by SAR control logic in digital. The logic is generally developed for a fixed kind of pattern of control signals with very minimal or no runtime modifiability. Failure to alter this pattern in effective ways prevents designer to find the optimal values of comparator parameters (e.g. accuracy, speed, power and area) to achieve best performance of ADC in and after first silicon. This paper describes the efficient programmable SAR control generation architecture which provides flexibility to modify the control pattern on silicon by minimal configuration to help finding the optimal pattern for the comparator to get best performance metrics and to aid during silicon debug. It also benefits in avoiding re-spins, faster time-to-market of better solution and easy scalability/portability of the digital part for further design/technology node.

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Cost effective programmable solution for generation of SAR-ADC controls

Abstract

Analog to Digital Convertor (ADC) working in successive Approximation Register (SAR) method has mainly two phases for each conversion.  Sample and evaluation phase. Comparator works in evaluation phase. Comparator has multiple stages. The On and off period of different stages of comparator in evaluation phase plays important role to define the quality of ADC output. In general the on and off duration of each phase is defined by particular values of a specified set of control signals. The control signals are driven by SAR control logic in digital. The logic is generally developed for a fixed kind of pattern of control signals with very minimal or no runtime modifiability. Failure to alter this pattern in effective ways prevents designer to find the optimal values of comparator parameters (e.g. accuracy, speed, power and area) to achieve best performance of ADC in and after first silicon.  This paper describes the efficient programmable SAR control generation architecture which provides flexibility to modify the control pattern on silicon by minimal configuration to help finding the optimal pattern for the comparator to get best performance metrics and to aid during silicon debug. It also benefits in avoiding re-spins, faster time-to-market of better solution and easy scalability/portability of the digital part for further design/technology node.

 


Introduction

The Comparator in analog is the heart of a SAR-ADC. There are different architectures of comparator available. One of the popular architecture uses multiple stages for high speed operation. Each stage needs to work for a specified duration to generate correct output. The accuracy of the output is the main focal point of the designer. For any first-time-designed ADC in a new technology, it is very difficult for the designer to predict the exact duration of each or combined stages for a particular requirement of accuracy, speed, power and area that make it best for the technology to give desired accuracy and speed with optimal silicon area and power. Based on the simulation models available designer coarsely define those periods. During silicon evaluation designer needs to closely monitor the output of ADC to verify the functioning of comparator stages. It is then needed to be able to modify the periods of each stages at this point to check the nature of variation of ADC output with many iterations to bring out the optimal operation.   

To control the active period of each stage, a defined set of control signals are used. Particular values of the set of signals define the states in a stage. These are controlled by digital logic which generally designed for a particular technology for fixed pattern or with very minimal controllability.  This lacks the easy controllability of period of each stage at silicon.  Designer has to wait for next silicon for validating ADC output for any modification in the pattern...