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Method and apparatus to improve reliability of the ASIC by avoiding sudden current drop on system reset assertion

IP.com Disclosure Number: IPCOM000238906D
Publication Date: 2014-Sep-24
Document File: 6 page(s) / 421K

Publishing Venue

The IP.com Prior Art Database

Abstract

Nowadays, SoCs contain multiple cores, multiple hardware accelerators and multi-million gates. Such SoC can draw large amount of current in high performance mode. The current of this magnitude is supplied by voltage regulators placed on the printed circuit board (PCB). When the system is fully functional, with all the cores running application/software, the current consumption increases manifold. This rise in current causes more IR drop within Die, Package and on the board components. The voltage regulator raises the voltage supplied, to overcome this increased IR drop. If reset to the SoC is asserted, when the system is in high performance mode, the chip activity suddenly stops and clock controller, PLLs etc. are put into reset. This causes the current consumption in the device to fall steeply. The sudden fall in device current creates voltage spike at the device boundary. This voltage spikes will cause immediate or long term device failure. The proposed method handles the sudden current descent in the SoC, when system reset is asserted and system is drawing high magnitude current. The proposed scheme provides a flexibility to control the steep current drop by various options implemented within the design.

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Method and apparatus to improve reliability of the ASIC by avoiding sudden current drop on system reset assertion

Abstract

                Nowadays, SoCs contain multiple cores, multiple hardware accelerators and multi-million gates. Such SoC can draw large amount of current in high performance mode. The current of this magnitude is supplied by voltage regulators placed on the printed circuit board (PCB).

                When the system is fully functional, with all the cores running application/software, the current consumption increases manifold. This rise in current causes more IR drop within Die, Package and on the board components. The voltage regulator raises the voltage supplied, to overcome this increased IR drop.

If reset to the SoC is asserted, when the system is in high performance mode, the chip activity suddenly stops and clock controller, PLLs etc. are put into reset. This causes the current consumption in the device to fall steeply. The sudden fall in device current creates voltage spike at the device boundary. This voltage spikes will cause immediate or long term device failure.

The proposed method handles the sudden current descent in the SoC, when system reset is asserted and system is drawing high magnitude current. The proposed scheme provides a flexibility to control the steep current drop by various options implemented within the design.

Introduction                                                                         

As shown in the diagram, the voltage regulator supplies the current to multi core, multi million gate designs. The voltage regulators utilize voltage sense feedback from the SoC Die, to regulate the voltage at the device boundary. This scheme is shown in Figure-1, where Power Supply and Power Distribution Network (PDN) are implemented on Printed Circuit Board (PCB).

Figure - 1 Power Supply and Power Distribution Network (PDN)

The Board and Package Power Distribution Network (PDN) shown in the figure -3 consist of embedded/discrete capacitors and inductors. The voltage regulator consists of error amplifier and Analog to Digital Convertors (ADCs). The voltage is sensed from the SoC die and the difference from the expected voltage is detected as an error. This error is then used by the voltage regulator to increase/decrease the voltage supplied so that a constant voltage is maintained at the power supply rails of SoC die.

This mechanism continuously monitors the power supply sense signals and controls the voltage supplied by the voltage regulators, if the supply rails reaches above or below the threshold level programmed for that particular supply rail. This mechanism takes care of the voltage drop in board, package and die, so that the voltage at the die boundary remains in the specified permissible range.

When the system is fully functional, with all the cores running application/software, the current c...