Browse Prior Art Database

RUNNING GATE LEVEL SIMULATION AT BLOCK LEVEL

IP.com Disclosure Number: IPCOM000238909D
Publication Date: 2014-Sep-24
Document File: 7 page(s) / 601K

Publishing Venue

The IP.com Prior Art Database

Abstract

Verification at 40nm and below requires complex timing checks, large amounts of memory, and apps to handle design-for-test and low-power considerations. Therefore post-layout simulation constitutes a critical design step for timing closure of a complex SoC. Gate level simulation (GLS) is a step in the design flow where simulations are run over post routed netlist with timing path back annotated with design functionality intact. GLS run time for a large and complex SoC is huge. GLS bring up involves running a test multiple times and resolving issues such as missing xfilter, missing non-resettable flop initialization, false violations, etc. Each such run can take significant time before we can analyze and debug the simulation result. This hits the gate level bring up schedule badly.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 36% of the total text.

Running Gate level simulation at block level

Abstract 

Verification at 40nm and below requires complex timing checks, large amounts of memory, and apps to handle design-for-test and low-power considerations. Therefore post-layout simulation constitutes a critical design step for timing closure of a complex SoC. Gate level simulation (GLS) is a step in the design flow where simulations are run over post routed netlist with timing path back annotated with design functionality intact. GLS run time for a large and complex SoC is huge. GLS bring up involves running a test multiple times and resolving issues such as missing xfilter, missing non-resettable flop initialization, false violations, etc. Each such run can take significant time before we can analyze and debug the simulation result. This hits the gate level bring up schedule badly.


In such cases we need a way to get the GLS simulation results in a short time so that we can do faster GLS bring up. We propose a solution where GLS results can be obtained in very short time (time reduction by a factor of 10-20) using hierarchical gate level netlist.

Problem Description

Following are the main pain points of running GLS for a large and complex SoC:

 

  1. Long run time of the test (compile time as well as simulation time)
  2. Very big snapshot size due to large design and back annotated sdf (up to 100’s of GB)
  3. More number of tool crashes due to large design database.
  4. LSF problem, there are less number of slots for high usage job.
  5. Iterative nature of GLS runs.
  6. Large dump size which makes the debugging slow.

Following are the things we need:

  1. We want a way out to reduce GLS run time (and space requirement as well) so that we can bring up the test in short time and run it on full chip GLS when it is stable. By bring up, we mean resolving all block level issues such as missing xfilter or missing non-resettable flop initialization.
  2. We want to reproduce a given GLS run with minor changes in the stimulus/testbench quickly.

Proposed Methodology

We propose running GLS at block level using RTL vcd/vpd dump generated at chip level. We can create activity of all the inputs of a given module hierarchy from the VCD or VPD file in the form of verilog simple assignment file. If we bind this file with block level netlist & sdf and run the GLS simulation at block level, exactly same result will be produced which would have generated with full chip GLS.  Assuming we have hierarchical gate netlist, running block level simulation will not compile other hardened blocks and testbench files therefore compile and simulation time will be order of magnitudes faster than full chip level.  We can do minor changes such as addition of xfilter, non resettable flop initialization, addition of forces, programming changes at block level only and rerun the simulation. This will save the run time tremendously.

As shown in figure 1, first we generate VCD/VPD dump at full chip RTL which was used to generate gate netlist, then we can derive...