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Flexible Early Oscillation System

IP.com Disclosure Number: IPCOM000238911D
Publication Date: 2014-Sep-24
Document File: 4 page(s) / 134K

Publishing Venue

The IP.com Prior Art Database

Abstract

This paper introduces an oscillation system that has a flexible early startup structure. The design allows microcontroller systems to use the crystal oscillator clock at a very early stage and reduces system re-configuration time.

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Flexible Early Oscillation System

Abstract

This paper introduces an oscillation system that has a flexible early startup structure.  The design allows microcontroller systems to use the crystal oscillator clock at a very early stage and reduces system re-configuration time.    

Introduction

One mixed clock system that contains crystal oscillator, internal RC oscillator, FLL or PLL etc., is popular in microcontroller applications.  After power on reset, normally internal RC oscillator will be active as default clock source and provide clock to FLL/PLL or system after it is stable.  The crystal oscillator default to be disabled.   It will be enabled by user software after system initialization. 

After chip supply is powered up, POR and LVD circuit will be active firstly and release stable supply to MCU core logic. Then clock system will be active to enable default clock source.  After clock sources to flash are ready, the FLASH module will be release to activate.  Flash module will do initialization.  Finally reset will be de-asserted and CPU will fetch vector and instruction. After every actions are done, the crystal oscillator have possibility to startup if the instruction enable its control register bit. This spends long time and don’t be satisfied by some applications.

In order to fix this problem, we use some flexible solutions by NVM bit, OPT bit, package option, non-reset register bit and write-once bit to enable crystal oscillator as soon as early .  The oscillator will be startup early in reset cycle after core supply stability.

Design and Implementation

 The microcontroller with embedded flash has below common sequence after power on reset as illustrated in Figure 1.

                                        

Figure 1 MCU RESET CYCLE WAVEFORM

1.      Asserted por_reset firstly after power supply reach POR condition

2.      Asserted global reset ipg_hard_async_reset_b after power supply reach stability for full chip

3.      De-asserted por_reset firstly

4.      De-asserted global reset after chip initialization, such as clock activate, NVM initialization, IFR load, FOPT update etc.

5.      Exit reset cycle and fetch instruction

The method introduced in this paper is composed of several important components illustrated in Figure 2.

The IRC (internal oscillator) and XOSC (crystal oscillator) provide the basic clock source for peripheral modules and system (CPU and bus clock) with clock divider and multiplexer.   IRC and XOSC will have one as default clock source and enabled after POR reset.  The other can be enabled by instruction code after whole system has worked normally. The clock control will control all of clock enabling, selection, divider, configuration etc. This page is main about clock controller to enable non-default oscillator early for some peripheral modules. 

Figure 2 MCU Oscillation System Diagram

The below solutions will describe the detailed implementation about oscillator early enabling...