Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Structure and Method to connect FEOL devices through underlying contacts

IP.com Disclosure Number: IPCOM000238915D
Publication Date: 2014-Sep-24
Document File: 5 page(s) / 62K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a structure that implements pre-patterned crystalline Silicon (Si), Silicon Germanium (SiGe), or Silicon Carbon (SiC) lines embedded in crystalline oxides (REO) in order to make connections under the device via self-aligned selective epitaxial growth of the connecting vias. Later, remote or direct contacts can be made from the top with conventional Back End of Line (BEOL) processing.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 01 of 5

Structure and Method to connect FEOL devices through underlying contacts

M1 in Complimentary Metal-Oxide Semiconductor (CMOS) circuits requires minimum dimension lithography and non-selective deposition and polishing of metals. The problem is space between the gates and the height of the gates.

The novel contribution is a structure that implements pre-patterned crystalline Silicon (Si), Silicon Germanium (SiGe), or Silicon Carbon (SiC) lines embedded in crystalline oxides (REO). In this fashion, connections, both short and long depending on resistivity, can be made under the device via self-aligned selective epitaxial growth of the connecting vias. Later, remote or direct contacts can be made from the top with conventional Back End of Line (BEOL) processing.

The following figures illustrate the novel process flow.

Figure 1: Start with a substrate

Figure 2: Grow blanket epitaxial oxide

Figure 3: Grow blanket highly-doped Silicon (Si), Silicon Germanium (SiGe), or Silicon Carbon (SiC)

Figure 4: Grow blanket epitaxial diode

1


Page 02 of 5

Figure 5: Grow blanket updoped or doped channel Si, SiGe, or SiC

Figure 6: Deposit gate stack

Figure 7: Poly Reactive Ion Etching (RIE)

2


Page 03 of 5

Figure 8: High-K (HK) Etch

Figure 9: Si RIE

3


Page 04 of 5

Figure 10: sREO

Figure 11: sEO

4


Page 05 of 5

Figure 12: RIE Channel, REO, and Si

5