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Dielectric Liner for Through-Silicon Via (TSV) and Related Processes

IP.com Disclosure Number: IPCOM000238926D
Publication Date: 2014-Sep-25
Document File: 3 page(s) / 198K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to improve the Atomic Layer Deposition (ALD) process and produce higher throughput and yield with lower costs. The solution is a Plasma-Assisted Atomic-Layer Deposition (PAALD) batch process with a Silicon (Si) precursor and O radicals under atmosphere and at room temperature

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Title

Dielectric Liner for Through-Silicon Via (TSV) and Related Processes

Abstract

Disclosed is a method to improve the Atomic Layer Deposition (ALD) process and produce higher throughput and yield with lower costs. The solution is a Plasma- Assisted Atomic-Layer Deposition (PAALD) batch process with a Silicon (Si) precursor and O radicals under atmosphere and at room temperature

Problem

Traditional through Silicon vias (TSV) silicon oxide dielectric liner is deposited by a Chemical Vapor Deposition (CVD) process or Atomic Layer Deposition (ALD) process at elevated temperatures. In addition to the elevated temperatures, the current ALD process has low throughput. The current CVD solution is a combination of Sub- Atmospheric Chemical Vapor Deposition (SACVD) Tetraethyl Orthosilicate (TEOS) liner and Plasma-Enhanced Chemical Vapor Disposition (PECVD) oxide capping for moisture block. It has poor step coverage and requires a thick film, resulting in low throughput, high cost, and requires a thicker dielectric film in order to achieve good coverage at the TSV bottom. This causes an extended Chemical Mechanical Planarization (CMP) processing time and marginal uniformity. The cost is expected to increase for 3x50 due to the longer processing time to reach the same sidewall thickness, and then run into closing up at the top of the TSV due to long deposition times.

Figure 1: Problem sketch


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Figure 2: CMP non-Uniformity (problem, cont'd.)

Solution/Novel Cont...