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Programmability Methodology Application for Concurrent Circuit Design in Multiple Foundries

IP.com Disclosure Number: IPCOM000238927D
Publication Date: 2014-Sep-25
Document File: 8 page(s) / 527K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a concurrent circuitry design with multiple different foundries.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 54% of the total text.

Page 01 of 8

Title

Programmability Methodology Application for Concurrent Circuit Design in Multiple Foundries

Abstract

Disclosed is a concurrent circuitry design with multiple different foundries.

Problem

A method is needed to enable the use of programmable elements to allow a single circuit design to work concurrently for multiple semiconductor foundries using similar process nodes. This is in contrast to most traditional porting methodologies, in which the final design undergoes changes from one foundry to the other.

Current methods port the schematic and layout from one foundry to the other, which requires more design work for matching the product specifications.

The objectives for a new method are listed here.  Programmable elements may include:


- Metal Options

- Active Field Effect Transistor (FET) switch controlled by:
EFUSE

I²C

System Management (SM) BUS

Service Programming Interface (SPI)

Bond-Option

Joint Test Action Group (JTAG)

Electrically Erasable Programmable Read Only Memory (E²PROM)

 Reduction of development cost and time
- Single architecture

- Identical footprint

- Single layout floor-plan and effort
- Universal test-benches

 Minimizing the cost and time for planned dual source redevelopment  Reduction of silicon test and characterization


- Test-boards

- Universal test-vectors

 Reduction of debug and design re-spin time
- Fib effort

- Mask effort

- Time to market

Solution/Novel Contribution

The novel contribution is a concurrent circuitry design with multiple different foundries.

Method/Process


Page 02 of 8

With the concurrent design with different foundries, the approach is to keep the original design with foundry A, and then simulate and tweak the original design with foundry B. The method adds programmability as required using transistors, resistors, capacitors, diodes, etc. A Field Effect Transistor (FET) switch or metal option is used to trim the performance. The final schematic is copied from foundry B to foundry A. The appropriate programmability settings are simulated and the design in foundry A is verified. The layout starts with final schematic for foundry A, and is then migrated to foundry B.

Figure 1: Design Me...