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Custom Clock Cell Design for Robust Clock Routing

IP.com Disclosure Number: IPCOM000239005D
Publication Date: 2014-Sep-30
Document File: 4 page(s) / 844K

Publishing Venue

The IP.com Prior Art Database

Abstract

The paper presents the scheme of designing a custom clock cell. Clocks Cells in the IC Design are the clock registers, latches and the clock gating cells. We provide and discuss a method and scheme to design and use custom clock cells to provide clock pin access in the metal layer desired for clock Routing.

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Custom Clock Cell Design for Robust Clock Routing

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Abstract

The paper presents the scheme of designing a custom clock cell. Clocks Cells in the IC Design are the clock registers, latches and the clock gating cells. We provide and discuss a method and scheme to design and use custom clock cells to provide clock pin access in the metal layer desired for clock Routing.

Problem Statement

As the Widths and the Spacing between the interconnect metals are shrinking, the interconnect delays are play a dominant role with shrinking technologies. Also as the chip size decreases, it is very difficult to come-up a well defined equations/tables for few of the parameters such as thickness variation (due to chemical mechanical polishing) or line width variation because of optical inaccuracies. It is thus becoming increasingly difficult to model these variations and we need to account for these as much as possible in the design either by adding margins or by taking care in physical design. The Variation affects the clocks in the design most and the clock tree construction needs to be very robust.  The Effects of clock nets asymmetrically spread across layers can have adverse effects.

·         Susceptible to process variations

·         Complexity in Timing Closure for multiple corners

·         OCV variations at Silicon and possibly yield loss

The Clock Construction is generally done by the usage of

         - Usage of adjacent widest Metal Layers available in the used technology node (which offers minimum Resistance) 

         - Negligible usage of other layers (to limit Variation)

         - Usage of Non Default Rules such as Double Width Double Space or single space triple width

If it is warranted that the clock nets are routed in the desired layers as stated above with negligible usage of the other metal layers (which are more susceptible to process variation) the additional timing margins may be reduced. This may lead to a reduction of some timing corners to reduce turnaround time and effort.

The custom clock cells are used to address the problem of clock nets routed in the non desired metal layers which are more susceptible to process variation

Proposed Clock Cells Design

A Custom clock cell is proposed to provide clock pin access in the interconnect metal layer used for clock routing for the given technology node

·         Metal Pin geometries for the lower Metal Layers are custom routed to give access in the desired clock routing layer

·         The Lower Metal Geometries are routed to give best delay while keeping the usage of the lower metals to a minimum value

·         All these metal geometries are made part of standard cell lef and  the clock pin access  is now available in the desired clock routing layer

This implementation helps in solving for the following scenarios, namely

·         Reducing the process variation on the clock interconnects

·         Easier timing closure 

    Figure 1: Default Cloc...