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Simple Metal ECO Methods to Bypass Power Gates for Different Failures in Power Gating Logic

IP.com Disclosure Number: IPCOM000239007D
Publication Date: 2014-Sep-30
Document File: 9 page(s) / 218K

Publishing Venue

The IP.com Prior Art Database

Abstract

Power gating is indispensable in present generation multi-core SOCs with high performance and low power requirements to reduce the standby leakage power. In newer technologies and/or newer designs, there could be failures in power gating structure. This will prevent the power gated core from either powering-up or functioning properly, which will leave the complete core untested. These failures can occur in power gate enable tree (buffer and delay logic) or in power gates. Fixing the failures of power gating logic in a conventional power grid structure requires either to overhaul the power gating structure or bypass the power gating structure. Overhaul of the power gate structure needs base layer and metal layer changes, which takes lot of effort, time, and cost to implement, which delays the silicon testing and software evaluation. This still may not ensure healthy silicon. In this paper we propose a power grid structure and a single interconnect layer ECO method for bypassing the power gating structure that enables chip testing and software evaluation to be performed.

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Simple Metal ECO Methods to Bypass Power Gates for Different Failures in Power Gating Logic

Abstract

Power gating is indispensable in present generation multi-core SOCs with high performance and low power requirements to reduce the standby leakage power. In newer technologies and/or newer designs, there could be failures in power gating structure. This will prevent the power gated core from either powering-up or functioning properly, which will leave the complete core untested. These failures can occur in power gate enable tree (buffer and delay logic) or in power gates. Fixing the failures of power gating logic in a conventional power grid structure requires either to overhaul the power gating structure or bypass the power gating structure. Overhaul of the power gate structure needs base layer and metal layer changes, which takes lot of effort, time, and cost to implement, which delays the silicon testing and software evaluation. This still may not ensure healthy silicon.  In this paper we propose a power grid structure and a single interconnect layer ECO method for bypassing the power gating structure that enables chip testing and software evaluation to be performed.

Background

Power gate structures in state of the art multi-core SoC designs have a high number of power switches. Power gating can be implemented with header or footer cells. An example of HEADER cell abstract view and schematic is shown in figures 1a and 1b respectively. For a typical header type power gate cell, there are two supply pins, primary/always-on power pin is connected to continuous supply rail of an SoC, and secondary/gated power pin is connected to switched supply rail of a power gated core. Layout and schematic view of these connections are shown figure 2a and 2b respectively. For a FOOTER cell, There are two ground pins, primary or continuous ground and secondary or switched ground. Generally the power gates are laid out in row or column fashion for lesser power supply noise. Figure 3 depicts a schematic view of typical power gating topology.

VSS

 

VDD_ON

 

VDD

 

VDD_SW

 

VDD_G

 

EN

 

VDD_SW: Switched rail connection of the block to gated supply pin of power gate in M2

 

Power gating Enable

Signal connections

 

VDD_ON: Always –On power connection with stacked vias

from top layers

 

VDD_Gà(VDD_SW)

 

VDDà (VDD_ON)

 

EN

 
  

Fig. 3: Schematic view of Power gating structure in a power gated core

 

Failures in any of the power gates may hamper the silicon validation and the further activities like software evaluation. Probable reasons for issues like power-up problem or unexpected Power Integrity failures can be:

•      Issues with power gate Enable tree structure

•      Poor power gate layout design

•      Inaccurate modeling of  power gate parameters (like ON mode resistance, Idsat)

•      Optimistic power numbers used for estimating the power gates count.

•      Improper power gates distribution     

To address these failures with the conventional power grid structures, it is required to cha...