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Double sided stack chip package with all core power pins on top side to improve power distribution on high current chip and PCB designs

IP.com Disclosure Number: IPCOM000239023D
Publication Date: 2014-Oct-01
Document File: 6 page(s) / 445K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a design for a double-sided chip package with all high-current core power pin pads on the top side and the rest of the pin pads on the bottom side of the chip package. This improves power distribution performance on the high core power chip and printed circuit board (PCB) designs.

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Double sided stack chip package with all core power pins on top side to improve power distribution on high current chip and PCB designs

For existing high current chip packages, pin pad placement is as follows: all pin pads are placed on one side only (i.e. bottom side), normally all of the high current power pin pads are located in the center, and all signal pin pads are surrounded on the four sides of the chip package.

Because the high ampere current has to be delivered to the core power pins located in the center of the chip package, normally, at least two thick layers are allocated on the printed circuit board (PCB) stackup for the power polygons routing. Hundreds of signal pins and related ground pin pads surround the core power pins, and each has a through hole via

which passes through the core power planes. Thus, the power plane is drilled with hundreds of holes before it reaches the center of the chip package. This is exacerbated if there are hundreds of high-speed differential signal pairs; via anti-pads are required on all power and ground layers, which are cut more on the core power plane and ground layers.

Figure 1: Placement of core power pin pads

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More cuts on the core power plane and ground layers results in higher impedance on the power delivery network. This limits the total supply current, core power transient response performance, and power thermal behavior. There are a few drawbacks to such known solutions. The total supply current is limited because of many cuts on the copper plane. The core power transient response performance could be affected because of the higher impedance (inductance) in the loop. The higher voltage drop between the core power source (i.e. direct current-direct current (DC-DC) power modules) and chip package, results in higher power loss and reduces the total power efficacy. Generated heat increases because of the higher power loss, and may need more air flow in the system design. Not all bulk decoupling capacitors can be placed close to the core power pin field, which also affects the core power transient response performance. This also results in a higher PCB cost because at least two thicker layers are allocated on the PCB stackup for routing power polygons.

The novel contribution is a design for a double-sided chip package with all high-current core power pin pads on the top side and the rest of the pin pads on the bottom side of the chip package. The power distribution performance can be improved on the high core power chip and PCB designs. Computer servers, embedded and top of rack switches, and any systems designed with high core power chips (e.g., Central Processing Units (CPUs), Broadcom Ethernet switches) can benefit from this kind of double-sided chip package.

The novel design comprises:

• Double-sided chip package • Multi-layer copper belts used to deliver the high ampere current from the core power source (i.e. DC-DC power modules) to the core power pins on...