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Stressing of redundant memory bits during burn-in test

IP.com Disclosure Number: IPCOM000239044D
Publication Date: 2014-Oct-03
Document File: 2 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

This document describes a circuit for producing uniform stress on all memory logic during burn-in test using memory built in self-test (MBIST) that doesn’t require a change in memory design. Devices under burn-in stress can have repaired or non-repaired memories. If a device has a repaired memory then only the selected redundant columns (or rows) of memory will be accessed during the burn-in stress and the un-used remaining redundant columns (or rows) will not be accessed, which will leave certain portions of the memory un-stressed. Similarly, for a non-repaired memory, all of the redundant columns (or rows) are left un-stressed. This translates into an inability to repair a device after burn-in and infield repair. If in-filed repair or repair is attempted, it will expose unstressed logic, which is a reliability concern.

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Stressing of redundant memory bits during burn-in test

Introduction

This document describes a circuit for producing uniform stress on all memory logic during burn-in test using memory built in self-test (MBIST) that doesn’t require a change in memory design.

Problem Statement

Devices under burn-in stress can have repaired or non-repaired memories. If a device has a repaired memory then only the selected redundant columns (or rows) of memory will be accessed during the burn-in stress and the un-used remaining redundant columns (or rows) will not be accessed, which will leave certain portions of the memory un-stressed.  Similarly, for a non-repaired memory, all of the redundant columns (or rows) are left un-stressed.  This translates into an inability to repair a device after burn-in and infield repair.  If in-filed repair or repair is attempted, it will expose unstressed logic, which is a reliability concern.

Proposed Design

A circuit that is active during MBIST burn-in mode and enables access to every redundant column or row) of memory during the burn-in run.  This circuit allows for uniform stressing of all redundant columns (or rows).

The proposed circuit has the following components:

  1. Event detector: detects the completion of selected March Algorithm run of MBIST during BURNIN.
  2. Repair data logic controller: Changes the data loaded into the repair data register after completion of each full MBIST run to ensure a uniform stress distribution.

Repair information is loade...