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Verification Methodology for Power Architectures Using System Modeling

IP.com Disclosure Number: IPCOM000239046D
Publication Date: 2014-Oct-03
Document File: 4 page(s) / 415K

Publishing Venue

The IP.com Prior Art Database

Abstract

The complexity of SoC architecture is increasing these days. Past products had a pin for voltage input but now we have a combination of internal and external voltage regulation (with multiple voltage levels) offered on the same IC along with a requirement that the SoC be power sequence independent. Customers also demand seamless mode transition between nominal and low power modes in which regulators are turned ON/OFF through a specific power sequence. Residual startup (battery dropout EMC test) is a critical failure mechanism that is unexplored in the AMS (analog-mixed signal) verification realm. Internal regulators are bypassed with LVDs masked in test architectures. Traditional method of verification is inadequate with respect to these issues and hence poses risk to functionality if not verified. Hence, there is a need to verify all possible configuration modes in power architectures by modeling the external regulation system using novel verification methodology.

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Verification Methodology for Power Architectures Using System Modeling

Abstract

The complexity of SoC architecture is increasing these days. Past products had a pin for voltage input but now we have a combination of internal and external voltage regulation (with multiple voltage levels) offered on the same IC along with a requirement that the SoC be power sequence independent. Customers also demand seamless mode transition between nominal and low power modes in which regulators are turned ON/OFF through a specific power sequence.  Residual startup (battery dropout EMC test) is a critical failure mechanism that is unexplored in the AMS (analog-mixed signal) verification realm. Internal regulators are bypassed with LVDs masked in test architectures. Traditional method of verification is inadequate with respect to these issues and hence poses risk to functionality if not verified. Hence, there is a need to verify all possible configuration modes in power architectures by modeling the external regulation system using novel verification methodology.

Background

Verification of a SoC having complex power management architecture requires testbench voltage drivers to behave similar to the customer’s board regulator.  Hence, we modeled a board power supply network (parameterized Verilog AMS board regulator model) with the following capabilities:

-          Bandwidth and damping factor control

-          Multiple supply voltage output in user defined (on the fly) network reconfiguration

-          External POR/LVD modeling (external supply diagnostic indicators): in case of supply outside its operational range and/or supply contention

-          Automatic current load changes based on POR/LVD sensing in the design

Also, at the time of ignition, there is a surge of current flowing into the SoC, hence, a droop/undershoot appears on the input supply voltage.  Sometimes this undershoot can go below the Low Voltage Detect (LVD) or Power On Reset (POR) thresholds.  Although the SoC can go into RESET, it is expected to come out of RESET as soon as the supply reaches its regulation level.  However, this may not happen for many reasons, such as LVD latch up or an absence of discharge path of residual charge.  This is called Residual startup issue, and customers do Battery Dropout EMC teststo checking this issue. Hence, it is important for the SoC reset automated AMS verification method to verify battery dropout EMC test. The proposed work contains:

-          Stimuli generator for 10 V car battery

-          Algorithm for handshake between design and power supply model to detect PASS/FAIL conditions

Board Power Supply Network

Figure 1: Buck converter (Voltage mode)

The proposed network model uses the Buck converter (voltage mode) shown in Figure 1 to step down the voltages. All the circles in Fig. 1 are parameterized. Hence, this model can be used to vary the bandwidth and damping factor control, regulation level, and current source capacity, which can be selected according to the regulator used by the c...