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Method and System for Improving Trap Rich Characteristics of RFSOI substrates with Multiple Layers of Polysilicon under the Buried Oxide

IP.com Disclosure Number: IPCOM000239172D
Publication Date: 2014-Oct-19
Document File: 2 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for improving trap rich characteristics of Radio Frequency Silicon on Insulator (RFSOI) substrates with multiple layers of polysilicon under the buried oxide.

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This is the abbreviated version, containing approximately 51% of the total text.

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Method and System for Improving Trap Rich Characteristics of RFSOI substrates with Multiple Layers of Polysilicon under the Buried Oxide

Trap rich substrates have been used to improve the performance of Silicon on Insulator (SOI) wafers for radio frequency (RF) applications. One of the challenges in producing trap rich SOI wafers is that during the high temperature processing required to fabricate the SOI wafers themselves as well as devices and circuits, the polysilicon layer can recrystallize. If recrystallization occurs, the benefits of the trap rich layer are lost. Trap rich layers are used to improve desirable electrical performance parameters of SOI substrates used for RF applications. The substrates use a layer of polysilicon underneath the buried oxide as illustrated in fig. 1.

Figure 1

The polysilicon layer provides lower carrier mobility (relative to single crystalline Silicon) as well as a high density of electrical traps which tie up any free carriers. The lower carrier mobility and trapping reduces the response of the base wafer to RF electrical fields present in the circuits in the active layer of the SOI structure. The coupling/response creates undesirable effects (harmonic distortion) which need to be minimized.

Disclosed is a method and system for improving trap rich characteristics of SOI wafers

with multiple layers of polysilicon under the buried oxide.

In accordance with the method and system, a trap rich structure with two or more layers of polysilicon which are separated from the base wafer and each other by layers of dielectric material is provided as illustrated in fig. 2.

1


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Figure 2

As illustrated, each of the two or more polysilicon layers is separated from the polysilicon layer above or below by using a t...