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Low Voltage Level Shifter Design for Reducing Logic Contention

IP.com Disclosure Number: IPCOM000239272D
Publication Date: 2014-Oct-24
Document File: 3 page(s) / 82K

Publishing Venue

The IP.com Prior Art Database

Abstract

A low voltage level shifter design is disclosed for reducing logic contention and improving voltage rise and fall delay while minimizing power consumption.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 71% of the total text.

Page 01 of 3

Low Voltage Level Shifter Design for Reducing Logic Contention
Level shifters are used extensively in multiple supply designs. Traditionally, level conversion is based on a proper design of driving strength between pull -up and pull-down networks.

FIG. 1 is a single supply level shifter design.

Figure 1

In accordance with the FIG. 1, the single supply level shifter design experiences a tradeoff between voltage rise delay and current leakage.

FIG. 2 is a Differential Cascode Voltage Switch (DCVS) level shifter design.

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Page 02 of 3

Figure 2

In accordance with the FIG. 2, the DCVS level shifter design experiences a balanced voltage rise and fall delay and current leakage stays relatively stable at low operating voltages. However, there is placement issue of a second supply in the DCVS level shifter design.

In the above described low level shifter designs, logic contention causes an increase in delay and power consumption. Therefore, there is a need to reduce the logic contention in level shifters and minimize the voltage rise and fall delay while minimizing power consumption.

Disclosed is a low voltage level shifter design for reducing the logic contention and improving the voltage rise and fall delay while the minimizing power consumption .

FIG. 3 is the low voltage level shifter design for reducing logic contention.

FIG. 4 illustrates input and output waveforms of the low voltage level shifter design .

Figure 3

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Page 03 of 3

Figure 4

In accordance with FIG. 3,...