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A Device and Method for Eliminating Redundant Hardware by Utilizing a Vectorized Fixed Point Multiplier

IP.com Disclosure Number: IPCOM000239274D
Publication Date: 2014-Oct-24
Document File: 6 page(s) / 228K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a device and method for eliminating redundant hardware by utilizing a Vectorized Fixed Point Multiplier (VFPM), which is capable of performing a multiply-accumulation operation. The VFPM is also able to divide input operands into vector elements of various sizes, which may include but need be limited to four identical building blocks. The identical building blocks can have common width for all operands, such as one 32bit, two 16bit or four 8bit operations. Here, the vector elements are handled on a same tree to eliminate redundant hardware, save power and reduce area occupied on chip.

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A Device and Method for Eliminating Redundant Hardware by Utilizing a Vectorized Fixed Point Multiplier

Disclosed is a device and method for eliminating redundant hardware by utilizing a

Vectorized Fixed Point Multiplier (VFPM), which is capable of performing a

multiply-accumulation operation. The VFPM is also able to divide input operands into vector elements of various sizes, which may include but need be limited to four identical

building blocks. The identical building blocks can have common width for all operands, such as one 32bit, two 16bit or four 8bit operations. Here, the vector elements are handled on a same tree to eliminate redundant hardware, save power and reduce area occupied on chip.

Fig. 1 illustrates a method of multiplying input operands.

Figure 1

As shown in fig. 1, the device performs a multiplication operation of any two operands such as operand A and operand B to produce a result D. Also, the device performs a multiply and accumulated operation by adding a third operand C to the product of operand A and operand B. Further, the multiply and accumulation operation is performed to produce a result D. Fig. 2 illustrates a method of dividing operands into two or three modes.

Figure 2

As shown in fig. 2, the input operand vectors are subdivided into three modes such as

word mode, halfword mode and byte mode. In case of word mode, the multiplier performs four 32-bit operations as represented in first table. In case of halfword mode, the multiplier performs eight 16-bit operations as represented in second table. Further,

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in case of byte mode, the multiplier performs sixteen 8-bit operations as represented in third table.

Fig. 3 illustrates a method of accommodating the three modes of operands in four identical cells.

Figure 3

As shown in fig. 3, pointers 304, 305, 306 and 307 indicate four identical cells cell 0, cell 1, cell 2 and cell 3 respectively, which receive 32-bits from each of the three operands. Here, the three operands are indicated with pointer 301 to operand A, 302 to operand B and 303 to operand C. Subsequently, each cell is capable of performing one 32-bit operation, two 16-bit operations and four 8-bit operations to produce the result D. Here, the output result D is indicated with a pointer 308.

Fig. 4 illustrates multiplication operations performed by each cell.

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Figure 4

As shown in fig. 4, a 32-bit operand A0 is multiplied with 32-bit operand B0 in the word mode to produce a 64-bit result D0. Further, in case of halfword Mode, a 16-bit operand

A0 is multiplied with 16-bit operand B0 to produce a 32-bit result D0. Subsequently, a 16-bit operand A1 is multiplied with 16-bit operand B1, to produce the other 32-bit result D1. Here, the halfword mode performs two independent multiplication operations with separate results. Later, in case of byte mode, an 8-bit operand A0 is multiplied with operand B0 to produce a 16-bit result D0. Subsequently, an 8-bit operand A1 is mult...