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A Novel Method for Efficient Early Analysis of a Design

IP.com Disclosure Number: IPCOM000239283D
Publication Date: 2014-Oct-27
Document File: 4 page(s) / 61K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for efficient early design analysis by enabling the use of backend tools for analysis in RTL space, using virtual logic netlists.

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Page 01 of 4

A Novel Method for Efficient Early Analysis of a Design


1. Introduction

During the design cycle of a chip, analysis for different criteria is done iteratively as the design cycle progresses. Early analysis of design criteria enables a bigger impact on the design and achieving its target. Also, early in the design cycle complete design information is not necessarily available. This necessitates solutions that enable efficient and early analysis even on partial designs. Additionally, analysis of certain criteria is more dependent on the micro-architecture and logic implemented in a hardware description language (HDL), which is available earlier in the design cycle, but has equal implications on the backend design team, later in the design cycle.

Solutions which enable early analysis of such criteria, but which are consistent with the solutions that result from complete analysis of the design, with extensive physical design information, is required. An example of such analysis is workload-driven clock gating analysis and rollup. Clock gating analysis is primarily dependent on logical graph which is available much earlier in the design cycle but has a significant bearing on the total chip power. Enabling clock gating analysis early in the logic design cycle allows for rapid logic changes to improve clock gating and meeting the clock gating targets.

Prior approaches for early RTL analysis are done using either 1) probability or formal based techniques 2) logic synthesis and physical design (PD) based backend tool engines. Analysis based on probability and formal based techniques have the limitation of being non-repeatable. GateAlert [1] uses this approach to analyze an input RTL or netlist for clock gating opportunities and output alternative clock-gating functions. However, each time GateAlert might return different sets of gating functions and thus the results are not repeatable, and thus making it difficult for the chip design teams to act on the said opportunities. Calypto's PowerPro [2] also uses probability and formal based techniques for analysis on pre-synthesis RTL. PowerPro is based on Calypto's Sequential Analysis Technology [3]. Statistical High-level Analysis and Rigorous Performance Estimation, SHARPE, [4, 5] is a tool that introduces statistical reasoning in the RTL verification paradigm by incorporating empirical statistical evidence from the lower levels of design. Here, RTL designs are represented using statistical models and a probabilistic model checking tool is then used to compute quantitative performance estimates. Probability or formal based solutions does not enable the use of existing PD-netlist based backend tools for analysis in the logic design space. This means, an additional investment is required for EDA companies to build separate tool chains in both RTL and PD-netlist spaces. Also, these are standalone solutions in the logic design space which can be easily get disconnected from solutions in the backe...