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Characterization and Parallel receiver testing of multiple lane transceivers using external loopback

IP.com Disclosure Number: IPCOM000239294D
Publication Date: 2014-Oct-27
Document File: 5 page(s) / 243K

Publishing Venue

The IP.com Prior Art Database

Abstract

We propose a methodology to automate test and characterize multiple lanes simultaneously on the same test bench with a focus on receiver testing such as receiver jitter tolerance, and receiver sensitivity. The methodology includes automated test and characterization of the receiver on multiple lanes, parallel testing and characterization of lanes using power splitters, and sequential testing using multiplexers on single test bench. The advantage of this method is that it allows faster time to market with maximum test coverage of transceiver or system on chip having transceiver, and saves considerable cost and time in making multiple setups.

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Characterization and Parallel receiver testing of multiple lane transceivers using external loopback

Abstract

We propose a methodology to automate test and characterize multiple lanes simultaneously on the same test bench with a focus on receiver testing such as receiver jitter tolerance, and receiver sensitivity.  The methodology includes automated test and characterization of the receiver on multiple lanes, parallel testing and characterization of lanes using power splitters, and sequential testing using multiplexers on single test bench. The advantage of this method is that it allows faster time to market with maximum test coverage of transceiver or system on chip having transceiver, and saves considerable cost and time in making multiple setups.

Introduction

These days, most transceivers are multiple lanes.  The number of lanes can vary from 1 to 16 or even more.  The receiver characterization and testing of all of the lanes across process, voltage and temperature (PVT) is difficult and time consuming with so many lanes. Current methods considered for testing of receiver with multiple lanes include:

·         Run sanity test on all of the lanes and identify the worst lane to do characterization across PVT;

·         Test one lane at a time – this is time consuming activity for validation;

·         Make multiple setups to test each lane – this requires multiple boards, multiple high end equipment, and high cost.

The proposed methodology is to do automated test and characterization of multiple lanes in parallel or sequentially on a single test bench with focus on receiver testing such as receiver jitter tolerance, receiver sensitivity, etc.  Important feature include:

·         Automated test and characterization;

·         Parallel testing and characterization of lanes using power splitters; and

·         Sequential testing using multiplexers and switches on a single test bench.

The benefits are faster time to market by characterizing or validating lanes in parallel, maximum test coverage before part goes to customer, and saving money, time and resource by running a single test bench instead of multiple test benches

Test Setup and Description

The block Diagram shown on Figure 1, is for a single test bench. It includes:

·         Device under test (DUT) having multiple lane transceiver that needs to be characterized having pattern generator and checker.

·         Test bench includes set of equipment such as programmable...