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Low Latency Level Translation Technique for High Performance Systems

IP.com Disclosure Number: IPCOM000239309D
Publication Date: 2014-Oct-28
Document File: 2 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use a level shifter to determine the power rail for which the driving logic should be connected, instead of using it for actual signal transition.

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Low Latency Level Translation Technique for High Performance Systems

Referring to Figure 1, Scenario 1 illustrates a logic block in lower Virtual Device Driver (VDDL) driving logic block(s) in a higher VDD (VDDH) domain. Assume that the difference between VDDL and VDDH is small enough for the logic block (s) on VDDH to still evaluate. The problem is that when logic on VDDL is driving logic 1, it is causing static leakages for logic on VDDH. Scenario 2 removes the static leakage by placing a level shifter in between the logic blocks. However, unwanted delay is introduced.

Figure 1: Illustration of the problem

The observation is that when the output of the VDDL block is high , it needs to be up-converted to VDDH to cause significant static power increase. The novel method achieves this by using the level shifter output to switch the power rail of VDDL logic block between VDDH and VDDL.

Figure 2: Illustration of the solution

Figure 3: Example embodiment

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