Browse Prior Art Database

Off--Chip Parallel Plate Capacitor using Insulated Cu Pillars

IP.com Disclosure Number: IPCOM000239343D
Publication Date: 2014-Oct-31
Document File: 5 page(s) / 649K

Publishing Venue

The IP.com Prior Art Database

Abstract

With increased frequency of operation, SoC are facing signal and power integrity issues. To address this issue, on die decaps are used to smoothen the power lines during circuit switching. These decaps occupy precious silicon area. We propose an implementation in which these decaps are implemented off-die using copper plates that are connected to circuitry through insulated copper pillars. These decaps are suitably placed over the switching circuitry so that they are electrically very near to the circuitry.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 91% of the total text.

Off--Chip Parallel Plate Capacitor using Insulated Cu Pillars

With increased frequency of operation, SoC are facing signal and power integrity issues. To address this issue, on die decaps are used to smoothen the power lines during circuit switching. These decaps occupy precious silicon area. We propose an implementation in which these decaps are implemented off-die using copper plates that are connected to circuitry through insulated copper pillars. These decaps are suitably placed over the switching circuitry so that they are electrically very near to the circuitry.

Fig. 1 shows the architecture of an integrated circuit (die) connected to off-die decoupling capacitors (decaps) using copper pillars.

Fig 1: Parallel Plate Capacitor Implemented using Cu plates and connected through insulated Cu pillars

Assembly

The structure can be thought of as a combination of two structures, as shown in Fig. 2.

Fig 2:  Structures forming the assembly

Lithographic Steps to realize Assembly I

Capacitance Calculations

The laminated metal sheets used as power and ground plate attached to the die area ~ 10mmx10mm. The lamination is an adhesive with min thickness of 12um and dielectric constant 5.2.

Fig 3: Parallel Plate Capacitor

With C= (ɛ0ɛr x A )/d,    Ɛ0=8.85x10-12 F/m  Ɛr=5.2, A=10x10 mm2 d= 12um

Cdf=0.384 nF

The plates can be stacked to increase the capacitance value.

Fig 4: Stacking of plates to increase the cap value

Proposal II: Power Connectivity

Power supplies can be connect...