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Method and Apparatus to Verify a Hardware Design using an FPGA Platform with Intelligent Load Leveler Capabilities

IP.com Disclosure Number: IPCOM000239377D
Publication Date: 2014-Nov-03
Document File: 3 page(s) / 49K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a method for verifying a hardware design using an FPGA platform with intelligent load leveler capabilities.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 95% of the total text.

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Method and Apparatus to Verify a Hardware Design using an FPGA Platform with Intelligent Load Leveler Capabilities

As hardware designs get larger and more complex, the harder it gets to verify these designs. Part of the issue is designs become so large that traditional software-based hardware simulators take far too long to hit enough test cases. As an example, during the last design some tests (of hardware that was just a subset of a larger design) took a week or more to run. This is not a reasonable turnaround for a designer who needs feedback on a daily basis in order to make progress. The other part of the issue is that the complexity of the design hinders test creation/coverage. As designs call for more units, auxiliary processors, levels of cache, etc., the harder it is for verification engineers to cover all the possible cases (especially with a limited number of engineer resources).

    To help alleviate some of these problems during the last design, an FPGA-based testing environment was developed (see the figure below). This allowed for running through tests that would take weeks in just fractions of a second (in some cases running 2000 tests/second). Other companies already use FPGAs, but there is lots of manual operation that can still be slow and time-consuming. A setup was created that is similar to a load leveler pool in which multiple mixes of tests, save outputs/fails, and resubmitting new tests without manual intervention were run (much faster test...