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Method and structure for forming junctionless FET with well-controlled channel thickness

IP.com Disclosure Number: IPCOM000239404D
Publication Date: 2014-Nov-05
Document File: 2 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a method and structure for forming a junctionless FET Field Effect Transistor (FET) with a well-controlled channel thickness.

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Method and structure for forming junctionless FET with well -controlled channel thickness
A junctionless Field Effect Transistor (FET) is touted as a viable device option for future Complimentary Metal-Oxide Semiconductors (CMOSs) due to the potential lower source/drain (S/D) resistance (junctionless).

A problem with junctionless FET is the electrostatics control.

The novel contribution is a method and structure for forming junctionless FET with a precisely controlled channel thickness.

The process is illustrated in the following figures.

Figure 1: Start with an Extremely Thin Silicon on Insulator (ETSOI) substrate

Figure 2: (a) Epitaxy growth of in-situ doped Silicon Germanium (SiGe), (b) Anneal to diffuse dopants into ETSOI layer

Figure 3: (a) Form dummy gate, (b) Inter-Layer Dialectric (ILD) deposition (dep)

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Figure 4: Remove dummy gate

Figure 5: Anisotropic SiGe etch selective to Silicon (Si) (e.g., by H2O2)

Figure 6: Form High-K Metal Gate (HK/MG)

This process enables precise channel thickness control (predetermined by the original ETSOI thickness).

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