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Method for Reducing Contact Resistance by Forming Dual Damascene

IP.com Disclosure Number: IPCOM000239405D
Publication Date: 2014-Nov-05
Document File: 3 page(s) / 88K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for reducing contact resistance by forming dual damascene for eliminating barrier layers.

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Method for Reducing Contact Resistance by Forming Dual Damascene

In general, there is a faster increase in via resistance than line resistance. Modeling operation indicates that the faster increase in via resistance is mainly due to Tantalum Nitride (TaN) at via bottom. So, there is a necessity to develop an efficient method to reduce contact resistance by eliminating barrier layers.

Disclosed is a method for reducing contact resistance by forming dual damascene thereby eliminating barrier layers. The method forms a dual damascene by increasing V0-M0 contact region as illustrated in Fig. 1.

Figure 1

In accordance with the method, tungsten at a width of 30 nm is used for increasing contact region between V0-M0. Accordingly, the increase in contact region between V0-M0 minimizes the contact resistance.

In one implementation, fabrication process begins by patterning metal to form CA/M0 substrate and sequentially depositing the layer of Titanium Nitride (TiN), a pulsed nucleation layer (PNL), and a color filter (CF) layer. Subsequently, filling of the Tungsten (W) is done till the height of V0 and followed by performing photoresist operation to open non-via regions. Thereafter, chlorine (Cl) or Boron (B) plasma etching is performed to remove W, TiN in non-via regions and low-k dielectric materials are deposited till the trench height. Further, patterning is performed to form M1 trench and high-bias Ta/TaN barrier is deposited to have thin bottom coverage and then us...