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Structure and method for microprocessor performance enhancement

IP.com Disclosure Number: IPCOM000239406D
Publication Date: 2014-Nov-05
Document File: 4 page(s) / 262K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a novel method for enhancing Atomic Layer Deposition (ALD) barrier nucleation on low-k trench sidewalls and retard nucleation on the Copper (Cu) bottom.

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Structure and method for microprocessor performance enhancement

Thick barrier-liner deposition at the bottom of the via increases via contact resistance limiting chip performance. Atomic Layer Deposition (ALD) barriers have been proposed to limit the effect of high-resistance material on interconnect performance, but experiments show that these barriers nucleate better on Copper (Cu) than on low-k films, rather than the desired reverse case.

The solution is a novel method for enhancing ALD barrier nucleation on low-k trench sidewalls and retard nucleation on the Cu bottom. Carbon Dioxide (CO2) treatment of ultra-low k enhances the nucleation of ALD Tantalum Nitride (TaN). In addition, Carbon
(C) is known to passivate the surface states of Cu, making it less reactive. This leads to selective barrier deposition by enhancing the growth rate on low-k and retarding nucleation of ALD TaN on Cu by single treatment.

The method comprises a C-based plasma treatment or gas-cluster treatment that is done on etched trench-via structure before barrier-liner seed deposition. This helps promote ALD TaN nucleation on low-k and retard nucleation on Cu. The plasma-based or the gas-cluster based treatment is done at room temperature. The gas-cluster based treatment can be done in a location-specific manner.

The process flow is:

1. Standard integration scheme till Reactive Ion Etching (RIE), wets to open up the trenches and vias in low-k/ultra-low-k dielectrics

2. Treat the Cu bottom...