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Silent Store Aware Storage and Checkpoint Management in Flash

IP.com Disclosure Number: IPCOM000239436D
Publication Date: 2014-Nov-06
Document File: 2 page(s) / 73K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to detect silent stores and upon detection reduce unnecessary writes to the cells, reducing write bandwidths, and thus improving the cell lifetimes.

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Silent Store Aware Storage and Checkpoint Management in Flash

In a flash storage system, the lifetime of cells is limited by the number of writes . In many applications, such as high-performance computing and numerical analysis, the same value is written to the same location several times. These repeated writes of the same values are called silent stores.

A method is needed to detect silent store in a flash storage system , enhance performance, and extend the lifetime of cells.

The novel contribution is a method to detect silent stores and upon detection reduce unnecessary writes to the cells, reducing write bandwidths, and thus improving the cell lifetimes.

The method comprises two main steps:

1. On a write request from host, read the corresponding address on the flash frame 2. Compare the data in the flash with the data from the write request ; if it is the same, then do not perform the write

Changes are needed in file system, because checkpoints appear logical as multiple,

when actually physical blocks are shared; allow copy on write. The drawback is that the comparison may get in the critical path of application checkpointing .

Figure 1: Hardware Flow chart -- Single-Level Cell (SLC) or Multi-Level Cell (MLC)-only,

with Dynamic Random Access Memory (DRAM) as cache

Example use case in High-Performance Computing (HPC) Checkpointing in Hybrid

Flash

1. Assume hybrid flash system of MLC (larger capacity) and SLC (faster and longer life time)

2. Checkpoints are a...