Browse Prior Art Database

Low Cost Method to Run RAM Test and SCAN Test Concurrently

IP.com Disclosure Number: IPCOM000239470D
Publication Date: 2014-Nov-10
Document File: 5 page(s) / 387K

Publishing Venue

The IP.com Prior Art Database

Abstract

In current IC design and test flow, RAM BIST test and scan test are general methods to confirm the quality of the devices. For products with RAMs, memory BIST is a general way to cover the array, but current BIST engines generated by third party vendors are quite large. In this paper we present a design including both RAM BIST test and scan test to reduce die area.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

      Low Cost Method to Run RAM Test and SCAN Test Concurrently

Abstract:

         In current IC design and test flow, RAM BIST test and scan test are general methods to confirm the quality of the devices.  For products with RAMs, memory BIST is a general way to cover the array, but current BIST engines generated by third party vendors are quite large.  In this paper we present a design including both RAM BIST test and scan test to reduce die area.

   

1.   Background

       Many new technologies and methods have been developed to reduce design cost.  Both test cost and die size are important design considerations, especially for low-end products.  In current designs, RAM and related RAM test logic (memory BIST) have been implemented in silicon to meet quality requirements.  Tests are run in a separate mode.  BIST logic is very complicated with a great number of standard cells, and additional test time is needed.  It would be advantageous to have a test architecture that takes up less die area with only minor loss of test quality. 

2.   Proposed test structure for combined scan and memory test

       In current IC design and test flow, RAM array and digital logic use different test methods to meet test requirements.  We propose a new test structure for combined SCAN and memory BIST test, which can reduce test cost and die area, and should be more effective in lost cost products.  The test structure is very simple and can be verified in RTL, and has no effect to back-end flow.  The test structure and method are illustrated in FIG. 1.

 

1)      Several scan chains 0…n to cover digital part;

2)      Different scan enable signals for digital scan chain(SE0) and memory scan chain(SE1), and both can be from same external source ---Ext_SE, which is shown in Fig.2;

3)      Memory RAM and its wrapper, and the wrapper will act as one scan chain; the wrapper is used to load write data and control signals for RAM array, and unload read data from RAM array;

                                      

                            FIG. 1   General test structure diagram

 

                           

                                    FIG. 2   SE generation diagram  

3.   Proposed design diagram for memory wrapper

       In the test structure, the most important part is the memory wrapper; the wrapper is designed as regular structure due to that bist algorithm is a regular operation shown below:

And scan test is also a structure test, so it’s possible to merge scan test and memory bist test through a dedicated scan wrapper for memory array; and the wrapper also works as a stand-alone scan chain, so it can be used to cover memory boundary fault or execute some bist algorithm fully through scan load/unload feature. The detailed structure can be seen in Fig.3. From the figure, some design items are listed:

...