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III-V semiconductor device with sharp junction and fill-friendly metal gate

IP.com Disclosure Number: IPCOM000239505D
Publication Date: 2014-Nov-12
Document File: 3 page(s) / 92K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a method and structure for forming III-V to simultaneously form a sharp junction formation and reduce gate resistance. The solution uses the sloped Raised Drain Source (RSD) to enable Replacement Metal Gate (RMG)/RSD overlap and tapered RMG to reduce gate resistance.

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-friendly metal gate

friendly metal gate

The compound semiconductor, III-V, is touted for future Complementary Metal-Oxide Semiconductor (CMOS) after Silicon (Si) technology due to high carrier mobility. One challenge of forming III-V devices is to bring junction close to the channel to reduce extension resistance; neither implantation nor dopant diffusion can be used for III -V.

-V semiconductor device with sharp junction and fill

V semiconductor device with sharp junction and fill -

III-

Another challenge of forming III-V is related to the replacement gate. As the gate length is highly downscaled, the gate opening after removing the dummy gate becomes so small that it can barely be filled with high-k gate dielectric and work-function metal (usually high resistance), leaving no room for low-resistance metal gate fill. Such a structure causes high gate resistance and thus degrades Alternating Current (AC) performance.

The novel contribution is a method and structure for forming III -V to simultaneously overcome two challenges in prior art: (1) forming a sharp junction formation, and (2) reducing gate resistance. The proposed solution uses the sloped Raised Drain Source (RSD) to enable Replacement Metal Gate (RMG)/RSD overlap and tapered RMG to reduce gate resistance.

The following figures represent the process flow for a III -V semiconductor device with a sharp junction and fill-friendly metal gate.

Figure 1: Starting with a III-V substrate such as III-V-OI or b...