Browse Prior Art Database

Timing Friendly Clock Gating/Divider Cell for Waveform Shaping

IP.com Disclosure Number: IPCOM000239525D
Publication Date: 2014-Nov-13
Document File: 7 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

Today’s SoCs involve multiple functional as well as test modes requiring the logic to work at a varying range of frequencies in multiple scenarios. Functional and DFT clocking may require a divided, bypassed or a punched clock under different scenarios. The conventional clock gating cell (comprising a latch and an AND gate) cannot generate a 50% divided clock. If the division is to be obtained through them, we have to use punched clock resulting in critical half cycle timing paths. Use of discrete cells or logic elements for punched and divided clocks often causes undesirable skew and OCV (on chip variation) uncertainties. Moreover, the clock select for such logic must have glitch-less clock switching and critical half cycle timing at full frequency.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 33% of the total text.

Timing Friendly Clock Gating/Divider Cell for Waveform Shaping

1.      Introduction

Today’s SoCs involve multiple functional as well as test modes requiring the logic to work at a varying range of frequencies in multiple scenarios. Functional and DFT clocking may require a divided, bypassed or a punched clock under different scenarios. The conventional clock gating cell (comprising a latch and an AND gate) cannot generate a 50% divided clock. If the division is to be obtained through them, we have to use punched clock resulting in critical half cycle timing paths. Use of discrete cells or logic elements for punched and divided clocks often causes undesirable skew and OCV (on chip variation) uncertainties. Moreover, the clock select for such logic must have glitch-less clock switching and critical half cycle timing at full frequency.

2.      Motivation

It would be advantageous to have a clock shaping cell with support for both punched and registered divided synchronous clocks providing improved timing parameters and requirements of clock gating cell. In this paper, we propose a design that makes optimum use of available resources to maintain and improve power and area compatibility while providing a wider range of functionalities.

3.      Clock Divider with Bypass & Stop Clock

The conventional structure uses a glitchless mux switching architecture with cascaded clock gating logic as shown in figure 1. It is used to generate 50% divided and undivided clocks in parallel. 

Figure 1: Conventional clock divider with bypass and stop clock

4.      Proposed Waveform Shaping Cell

Figure 2 is an abstract representation of a proposed single cell used for generating divided and punched clocks. SEL ad TE signals are used to select the clock generation scheme. The combination of these two select signals maps to any four of the following configurations shown in table 1. 

Figure 2: Proposed waveform shaping cell.

The configurations for the proposed cell are as follows:

·         Clock bypass mode:Free running input clock is propagated at the output.

·         Clock gating/stop mode: No clock is propagated and output is tied to low (logic 0).

·         Clock punched division: Enable based punched divided clock is propagated at output.

·         Clock registered or 50% duty cycle division: Register divided clock (50%DC) at output.

TE

SEL

DIN

CONFIG

0

0

!SEL

Gated Clock

0

1

!E

Punched Clock

1

0

!E

Registered Operation (50%DC)

1

1

!SEL

Bypass Clock

Table 1: Configuration map for proposed clock shaping cell.

The proposed cell can be segmented into three blocks, as shown in figure 3.

Figure 3: Proposed waveform shaping cell block diagram.

 The functionality of each of these blocks is described below.

·         Configuration Select :

This block is combinational logic that translates input DIN as per the cell’s operation configuration. The value of DIN is decided as per the input signals SEL, TE and E (shown in table 1).

·         Select Synchronizer:

Select synchronizer synchronizes the input select signal SEL w.r.t. t...