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Method to Ensure Planarity of 3D Photoresist

IP.com Disclosure Number: IPCOM000239581D
Publication Date: 2014-Nov-17
Document File: 1 page(s) / 21K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to ensure planarity in photoresists during deposition onto 3D chip stacks.

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This is the abbreviated version, containing approximately 54% of the total text.

Page 01 of 1

Method to Ensure Planarity of 3

In CMOS fabs, lithography utilizes spin-on photoresist, exposed by a high-precision stepper. Inherent in this approach is an assumption that the wafer surface is flat. Via the use of chemical mechanical planarization (CMP), integrated circuits usually are flat, at least to within the limits of spin coating models. Structures for 3D integration, on the other hand, often are not. Through-silicon vias (TSVs) drill deep into the silicon wafer, and a separate lithography step may be needed to open the bottoms of these vias. Interposers and redistribution wiring often have significant topography, with deep cavities and elevated wires. Researchers from the Fraunhofer Institute pointed out that the standard model for spin-on resist thickness breaks down if surface topography exceeds 40 microns. As the wafer spins, larger features act like boulders in a stream, with a thick accumulation of resist "upstream" and a low-coverage eddy "downstream." Interactions between adjacent features can lead to complex, non-uniform coating patterns. Spray coating of resists is one potential solution. Still, the viscosity and drying rate of the resist will affect coverage uniformity. Vertical features such as via or cavity sidewalls are very difficult to coat. If the resist is too viscous, it will dry before spreading over the entire surface; not viscous enough, and it won't adhere to vertical surfaces. Nor can a liquid resist bridge openings, as might be d...