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Quadrant based Instruction ID assignment for SMT (Simultaneous Multithreading) microprocessor

IP.com Disclosure Number: IPCOM000239611D
Publication Date: 2014-Nov-19
Document File: 3 page(s) / 45K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for quadrant based instruction ID assignment for SMT (Simultaneous Multithreading) microprocessors is disclosed.

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Quadrant based Instruction ID assignment for SMT (

((Simultaneous Multithreading

Simultaneous Multithreading ) microprocessor

microprocessor

Disclosed is a method for quadrant based instruction ID assignment for SMT (Simultaneous Multithreading) microprocessors.

For multiprocessor, the instruction ID for a thread is usually assigned from 0-N (N is the number of in-flight instructions). Each instruction ID usually has a thread ID with it to identify which thread it belongs to. For example, for 8 threads, then each instruction would carry 3-bit field with it to identify which thread it belongs to. The thread bits

would then travel through out the processor from Fetching to Completion, and consumes power and area. In this

disclosed method, the Instruction ID are assigned by quadrant, and by thread. The thread bits are also included in the instruction ID field so that the thread ID will not be needed to flow with the instruction to tell which thread it belongs to. By not flowing the thread bits with the instruction through out the machine, significant power savings and silicon savings occur. All of the comparators needed for flushing and completion will also be smaller since the thread ID field is no longer needed in the compares.

For an example of assigning the instruction by quadrant and by thread:

For a single thread, the instruction ID will be from 0-511 (for a 512 in-flight instructions).

For SMT2, one thread will have instruction ID from 0-255, while the other thread will have instruction ID from 256-511.

For SMT4, one thread will have instruction ID from 0-127, one thread will have 128-255, one thread will have 256-383, one thread will have 384-511.

For SMT8, the threads ID will be divided in half again ( see attached picture). The instruction ID are ranged from 0-63, 64-127, 128-191, 192-255, 255-319, 320-383, 384-447, an 448-511.

In an example embodiment, the instruction ID quadrant does not need to be tied to a specific thread ID. For instance, in SMT4, instruction ID 0-127 are not tied to thread 0, or instruction ID 128-255 are not tied to thread1. Rather instruction ID 0-127 can be assigned to any of the 4 threads, the same is true for the other instruction ID from the other quadrants. In order to achieve this, there will be a 3 bit field per thread (in SMT8) to identify which quadrant the thread does belongs to. For example, for quadrant 0 (instruction ID 0-63), a 3-bit field could contain a decimal value of 5, to indicate that any instructions with instruction ID of 0-63 belong to thread 5. If quadrant 1 (instruction ID 64-127) has a decimal value of 8 in it, it would indicate that any instructions with instruction ID from 64-127 belong to thread 8. This 3-bit field can be allocated when a thread is assigned to the processor. (SMT4 will only need 2 bits per thread to perform this function).

Instruction tags for a 512 entry ICT are currently 9-index bits plus a wrap bit. The ST/SMT mode determines how the ICT table is pa...