A Method and Structure for On-Chip Parallel Stressing and Integrating Components for Radio Frequency (RF) Reliability
Publication Date: 2014-Nov-19
The IP.com Prior Art Database
A method and structure is disclosed for on-chip parallel stressing and integrating components for Radio Frequency (RF) reliability.
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A Method and Structure for On - for Radio Frequency (
Disclosed is a method and structure for on-chip parallel stressing and integrating components for Radio Frequency (RF) reliability.
The method and system provides a capability to stress multiple devices on the chip in parallel in a RF stress configuration. The parallel configuration of the multiple devices on the chip greatly enhances productivity of a wafer stressing equipment. Here, the multiple devices are stressed in parallel and tested serially. As test time is insignificant compared to the stress time therefore, each device added in parallel increases equipment productivity. In some cases, the improved productivity corresponds to a difference between adequate data for making a clear decision and limited data requiring a significantly higher risk for making the decision.
The method and system provides a capability to integrate some external functions for an RF stress configuration onto the chip. The integration of the external functions enhances the simplicity and speed of the system setup to start testing. The external functions are also advantageous for implementing the parallel stressing. In a scenario, the integration of the external functions improves the data related to, such as, power detector. The method and system integrates multiple Device Under Tests (DUTs) to improve equipment productivity during stress and test. Here, switches are used to put the devices either in parallel with one another for stress or remove devices for test. The switches need to be highly conductive, with close to zero impedance, in on state with little reflection and highly resistive with ultrahigh impedance in off state for a given RF nature of the DUTs. In a scenario, the switches correspond to Micro Electromechanical systems (MEMS). Additionally, a control circuitry, such as, but not limited to, a serial address input, is required for controlling the switches.
In a scenario, DUTs are fabricated in close proximity each with three externally controllable switches, S, which are closed during stressing. All switches are open during test except the switches for the DUT actually under test at that time. Stress power is also applied in parallel as shown in fig. 1. The total number of parallel devices under RF stress in this scenario depends on the device size and stress drain-source current needed, N*Ids_stress ~ sqrt(Pw...