Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method and System for Achieving A Minimized Chip Size For Wafer Level Chip Scale Package (WLCSP) Structures By Placing Insulator Mask Level Design Shapes over Seal Ring Structures

IP.com Disclosure Number: IPCOM000239620D
Publication Date: 2014-Nov-19
Document File: 4 page(s) / 223K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for achieving a minimized chip size for Wafer Level Chip Scale Package (WLCSP) structures by placing insulator mask level design shapes over seal ring structures in a disposable KERF region.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 4

Method and System for Achieving A Minimized Chip Size For Wafer Level Chip Scale Package (

((WLCSP

WLCSP) )

Structures By Placing Insulator Mask Level Design Shapes over

             Structures By Placing Insulator Mask Level Design Shapes over Seal Ring Structures

A Wafer Level Chip Scale Package (WLCSP) is used in high volume production for packaging of semiconductor integrated circuit products that are very close to the size of the silicon die. A minimized semiconductor chip size for a WLCSP product is achieved

when a seal ring region is not exposed or contains etched metals in the seal ring region in the Back End of Line (BEOL) stack. Necessary design shapes are utilized to protect the seal ring region during the WLCSP process steps solely in the total chip design area. However, the design shapes result in a larger total chip size being needed. The last metal levels can also be removed from the seal ring region so that there isn't any metal level immediately below the WLCSP first metal level. The absence of metals avoids causing exposure or shorting between the WLCSP and seal ring metal due to insulator type materials in the seal ring region. A change in an interface film can also avoid exposure. However, the interface film for the WLCSP processing cannot be changed due to performance or other product or process or yield or reliability considerations. The resulting chip design may be of lower yield after the WLCSP processing is completed. The lower yield is due to misprocessing of the WLCSP levels above the total chip design area.

Disclosed is a method and system for achieving a minimized chip size for WLCSP structures by placing insulator mask level design shapes over seal ring structures in a disposable KERF region as illustrated in Figure 1.

1


Page 02 of 4

Figure 1

As illustrated in Figure 1, a reticle design WLCSP is checked to see if the seal ring

2


...