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Electrical KERF Measurement to Identify Substrate Slip During Semiconductor Wafer Processing

IP.com Disclosure Number: IPCOM000239621D
Publication Date: 2014-Nov-19
Document File: 5 page(s) / 219K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method of using capacitive and dielectric breakdown (shorting) electrical KERF measurements on semiconductor process defect monitor structures to identify the overlay (overlap) between two physical mask levels forming a gate oxide structure to represent wafer substrate slip during or after wafer processing.

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Electrical KERF Measurement to Identify Substrate Slip During Semiconductor Wafer Processing

During fabrication (fab), a wafer substrate slippage issue can occur during processing, primarily on Silicon on Insulator (SOI) wafers. This results in an excessive polysilicon overlay misalignment to silicon regions. Also known as PC to RX overlay, where PC refers to polysilicon and RX refers to or is also known as (but not limited to be) diffusions, this misalignment is not easily detected in electrical KERF structures tested prior to wafer shipment but is seen by the end client.

The novel contribution is a method of using capacitive and dielectric breakdown (shorting) electrical KERF measurements on semiconductor process defect monitor structures to identify the overlay (overlap) between two physical mask levels forming a gate oxide structure to represent wafer substrate slip during or after wafer processing.

The solution provides a way to have an electrical test method that consists of capacitance as well as breakdown type measurements, to compliment other known physical overlay measurement practices in the art, to validate whether the overlay of the polysilicon to silicon regions conforms to its maximum specification during the semiconductor manufacturing process. This method does not have a benefit over known physical measurement practices in the art, which is done ideally at sector just after the Polysilicon process is completed. However, this method is beneficial in that it determines whether excessive polysilicon overlay misalignment to silicon regions occurred that was not detected by the known physical measurement practices in the art.

This method also provides a wide range of electrical test data across a semiconductor

wafer. The data indicates whether the overlay of the polysilicon to silicon regions conforms to the maximum specification during manufacturing. This is done without performing costly traditional failure analysis techniques, such as cross sectioning or de-layerin...