Browse Prior Art Database

Method for Designing Fully Isolated Silicon Controlled Rectifiers (SCRs) on Bulk Wafers

IP.com Disclosure Number: IPCOM000239623D
Publication Date: 2014-Nov-19
Document File: 5 page(s) / 239K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for designing fully isolated Silicon Controlled Rectifiers (SCRs) on bulk wafers.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 5

Method for Designing Fully Isolated Silicon Controlled Rectifiers ( Wafers

Disclosed is a method and system for designing fully isolated Silicon Controlled Rectifiers (SCRs) on bulk wafers.

In accordance with the method, a thin layer of Silicon Germanium (SiGe) is deposited on a substrate. Subsequently, a silicon (Si) layer for a Field Effect Transistor (FET), an oxide deposition layer and a sacrificial layer containing compounds such as, a-Si, SiGe or Ge or SiN are deposited. Thereafter, narrow trench masks are created as illustrated in Figure 1.

Figure 1

Then, a trench etch followed by an undercut etch is performed in the [100] crystal direction. The central isolated strip in the x-section view is anchored to the substrate in the direction perpendicular to the page. As an optional step, an isotropic rapid thermal etching (RTE) may be performed by selectively etching SiGe to Si as illustrated in Figure 2.

1

) ((SCRs

SCRs)

on Bulk

on Bulk


Page 02 of 5

Figure 2

As illustrated in Figure 3, surface passivation is performed by using rapid thermal oxidation (RTO) or dry oxidation and Low Pressure Tetraethylorthosilicate (LP-TEOS) cavity fills or other dielectric films are utilized to fill the undercut etched sections and later, end-pointed oxide etching is performed. Subsequently, selective etching is performed to remove the sacrificial layer and optionally re-growing a gate oxide layer.

Figure 3

In one implementation, dimensions of each isolated section have a length about 10µm or less, width less than 1-3 µm, and a very thin Si thickness of about 1µm. A Shallow Trench Isolation (STI) and cavity-beneath filling are...