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Method for forming merged semiconductor regions on nanoscale transistors

IP.com Disclosure Number: IPCOM000239918D
Publication Date: 2014-Dec-12
Document File: 1 page(s) / 33K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a simple, highly selective method for interconnecting discrete semiconductor regions in close proximity to one another. The novel solution uses a catalytic agent selectively deposited on the discrete semiconductor regions to be merged.

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Method for forming merged semiconductor regions on nanoscale transistors

A major challenge facing the successful fabrication of three -dimensional (3D) transistor structures is the ability to combine discrete regions of semiconductor materials (e.g., the source and drain regions of fin Field Effect Transistor (FINFET) devices) into a common semiconductor region. The impetus for merging these initially separate regions is to simplify the subsequent contacting steps in addition to improving the access resistance of the devices.

Traditional methods for accomplishing this involve Chemical Vapor Deposition (CVD)-based epitaxial crystal growth. The major challenge for this approach is the diminishing process window for achieving selective growth on nanoscale features with sufficient doping incorporation and minimal feature perturbation (agglomeration).

A simple, highly selective method is needed for interconnecting discrete semiconductor regions in close proximity to one another.

The novel solution uses a catalytic agent selectively deposited on the discrete semiconductor regions to be merged. Subsequent exposure of the regions to a low-temperature semiconductor-hydride based gaseous environment leads to catalytically enhanced crystal growth from the semiconductor "seed" regions, ultimately merging the regions. The catalytic agent can be any number of metallic elements such as Au, Ag, Al, Sb, or other known catalytic agents. The deposition can easily be made selective...