Browse Prior Art Database

Pipeline Stalls Viewer

IP.com Disclosure Number: IPCOM000240129D
Publication Date: 2015-Jan-05
Document File: 4 page(s) / 140K

Publishing Venue

The IP.com Prior Art Database

Abstract

The embedded application optimization process is difficult and requires good knowledge of processor architecture, including how the instruction pipeline works. A system for visualizing the information available in the pipeline representation of a cycle accurate simulator complements other existing methods, such as profiling and logging, and helps embedded application developers and compiler engineers to better understand the instructions flow. Seeing the pipeline state at every cycle, with details about stalls cause, location and type, reduces the time needed in optimization process. Such a system can also be used during hardware architecture definition but also during simulator development, for resolving tricky inaccurate cycle reporting.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Pipeline Stalls Viewer

Abstract:

The embedded application optimization process is difficult and requires good knowledge of processor architecture, including how the instruction pipeline works.

A system for visualizing the information available in the pipeline representation of a cycle accurate simulator complements other existing methods, such as profiling and logging, and helps embedded application developers and compiler engineers to better understand the instructions flow. Seeing the pipeline state at every cycle, with details about stalls cause, location and type, reduces the time needed in optimization process. Such a system can also be used during hardware architecture definition but also during simulator development, for resolving tricky inaccurate cycle reporting.

Abbreviations and terms:

CAS - Cycle Accurate Simulator

GUI – Graphical User Interface

PC – Program Counter

RAW – Read After Write

RSU – Resource Stall Unit

VLES - Variable Length Execution Set

Description:

The proposed system for viewing the pipeline information comprises of an intuitive GUI with the following components:

1.      Pipeline view

·         Very intuitive colored graphic display with the pipeline content: PC, cycle, instructions (VLES) in each stage with details about inserted stalls and their cause.

·         Each instruction/stall type is colored differently for better visibility.

·         Displayed as a table in which each line represents the state of the pipeline at a certain cycle, and each column represents a pipeline stage, thus showing the pipeline history for a selected range of cycles/PC’s. This is presented in Fig. 1.

         Fig.1 Basic content of pipeline view

·         User has the option to select a simple or a complex-view. Both views contain information about cycle, pc and pipeline stages. In the simple one at every pipeline stage it is displayed the instruction in that stage or the inserted stall. The complex one brings extra information by displaying at each pipeline stage the instruction currently in that stage and the instruction state. The difference between the contents of the two views is presented in Fig. 2.

        Fig.2 Content of simple versus complex view

The state of a certain stage in the pipeline can be of several types:

o   Exec(the instruction is executed)

o   Stalled(the instruction is currently stalled)

o   Type of Stall (no instruction executed and a stall was inserted).  The stall type will be according to the used architecture. E.g. RSU (Resource Stall...