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Selectively Increasing Slew Limits to Optimize Power and Area While Still Satisfying Timing Constraints

IP.com Disclosure Number: IPCOM000240145D
Publication Date: 2015-Jan-06
Document File: 3 page(s) / 66K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to selectively increase slew limits on certain logic gates to optimize power and area while satisfying all of the timing constraints. The method proposes relaxing the slew limit for all non-critical circuits as long as the slack is above a certain threshold to reduce power, allowing many slew limits as long as there is sufficient positive slack.

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Selectively Increasing Slew Limits to Optimize Power and Area While Still Satisfying

Timing Constraints

Power consumption is a major design constraint in designing very large-scale integrated circuits (VLSI) such as high performance microprocessors. Circuit optimization is essential to perform power-performance trade-off. Reducing power and area, while satisfying timing constraints, is the ultimate goal of logic synthesis.

Various approaches have been utilized in logic synthesis for power savings [1-6]. Examples include substituting certain logic gates with higher threshold voltages [2-3], a dual-voltage design with high and low voltage gates [1].

With current physical synthesis flow, high performance designs such as microprocessors impose stringent slew limits on all logic signals. These slew limits are typically much tighter than the maximum slew limits for which the library cells used for the synthesis are pre-characterized. Having each gate satisfy the same slew limit causes excessive oversized gates and/or buffering used in the non-critical circuits, especially in circuits where high voltage (Vt) or low-Virtual Device Driver (VDD) devices are used.

Reducing power and area, while satisfying timing constraints, is
the ultimate goal of logic synthesis. Slew limits are imposed on
each gate. If this limit is relaxed for gates that have a slack
greater than certain threshold (e.g., 50%) of the cycle time,
then these gates can be sized with a smaller device width,
thereby decreasing area and power.

One method used today in logic synthesis is Vt assignment. To
reduce the critical path delay, low Vt circuits are used on the
critical path since they are faster than high Vt gates. On
non-critical circuits with excessive slack, high Vt circuits are
used. The use of high Vt devices on the non-critical circuits
allows leakage power savings.

In the dual-VDD design approach, circuit elements including
cells, latches, and macros are placed with high or low voltage
islands to minimize integrated circuit (IC) power while
maintaining overall performance. In this approach, however, the
low power circuits have to be clustered into low voltage islands
and then level-shifted up to high voltage regions.

In a typical physical synthesis flow, timing analyzers utilize
pre-characterized models for gate delays and slews. Each gate is
characterized with a maximum capacitive load that it can drive
and a maximum input slew rate. High performance designs, such as
microprocessors, typically impose much tighter slew limits on all
logic signals. The slew limit typically used for logic signals
is 1/3 of the cycle time. Each gate must satisfy the same slew

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limit. This can cause excessive gate width used in the

non-critical circuits, especially in circuits where high Vt or
low-VDD devices exist, since these circuits either must be
resized-up or be buffered to satisfy the slew limits. This is
wasted device width since if the slew limits were relaxed...