Browse Prior Art Database

Method to isolate interconnect faults using low resolution TDR hardware

IP.com Disclosure Number: IPCOM000240251D
Publication Date: 2015-Jan-15
Document File: 6 page(s) / 137K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is the use of low-resolution time domain reflectometry (TDR) to isolate failing interconnects. Using this enables a cost-effective hardware implementation to be integrated into a product and shipped with every system.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 32% of the total text.

Page 01 of 6

Method to isolate interconnect faults using low resolution TDR hardware

Disclosed is a method, currently implemented in software, that enables low-resolution time domain reflectometry (TDR) to isolate failing interconnects. The waveform analysis method described here allows TDR to be run with sampling samples as far apart as twice the minimum resolution requirement, which is typically multiple unit intervals [UIs]. Low resolution TDR can be cost effectively integrated into a product and shipped with every system. Isolating failing interconnects in a product reduces the time to service failing machines and reduces the number of parts that must be replaced when certain interface failures occur. This reduces repair time in manufacturing, service time in the field, and parts stocking requirements in the field. Previous known solutions use high-resolution TDR to isolate failing components. [*]

    This new solution uses low-resolution TDR to isolate failing components. It does this by gathering a TDR response, interpreting the response to determine a type and position of a fail, and using a look-up table to identify the failing component. This provides deterministic isolation of failures to particular components in a system without requiring prior swapping of parts or similar time and part intensive methods.

    The overall use in a computer system requires hardware as well as software. The following describes a software method which is used with the hardware. The method would work using any hardware having similar capabilities. Figure 1 below is an example of hardware logic showing TDR pattern generator to generate TDR pulse and sampling controller to sample level.

Figure 1

    The method uses the following steps:
1. Set up hardware to generate and measure pulse
2. Measure and record pulse response at required resolution
3. Interpret measurements as particular faults at particular distances from measurement

Method flow:

1


Page 02 of 6

point 4. Look up distance to fail in a table to find failing component or component boundary Steps 1 to 3 may be repeated for different fault types as needed. For example, due to hardware capabilities, one setup may be needed to measure a short to voltage and a different setup needed to measure a short to ground.

Alternative, reduced, modes:

    A reduced function, faster mode, may be accomplished by combining steps 2 and 4. In this case, the measurement would only be done at particular timing and voltage points based on the expected fault boundaries. In addition, a priori knowledge of the fault type, through, for example, some earlier wire test run, could be used to reduce the combinations of setups/measurements used.

Detailed step description:

    While the above two simplifications may be available, the following will describe the more complete method. This is still described in general, a specific implementation is described in a subsequent section. A flow overview is shown in Figure 2 below.

Figure 2

2


Page 03 of 6

Steps...