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CONTROLLING POWER ON SEQUENCE CRITICAL FOR HYBRID SILICON PHOTOMULTIPLIER

IP.com Disclosure Number: IPCOM000240255D
Publication Date: 2015-Jan-16
Document File: 3 page(s) / 36K

Publishing Venue

The IP.com Prior Art Database

Abstract

The present invention includes a technique for incorporating power on sequence and voltage ramp control on a silicon photomultiplier (SiPM). The technique includes electronic components on the SiPM to form a hybrid SiPM. The hybrid SiPM includes high voltage complementary metal oxide semiconductor (CMOS) wells and lower voltage control logic and/or amplifiers. A high voltage gate is placed in line with the SiPM cathode voltage. When the low voltage is off, the gate opens and there is no voltage applied to SiPM single photon avalanche diode (SPAD). A simple control circuit, for instance a resistor–capacitor (RC) circuit, is utilized to control ramp of low voltage to the gate.

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CONTROLLING POWER ON SEQUENCE CRITICAL FOR HYBRID SILICON PHOTOMULTIPLIER

BACKGROUND

The present invention relates generally to a hybrid silicon photomultiplier (SiPM) and more particularly to a technique for controlling high voltage power on a sequence for the hybrid SiPM.

Generally, an analog low voltage circuitry is present on a separate physical device. The analog low voltage circuitry is placed such that the circuitry is separated from a high voltage SiPM. An external control determines order of powering up of SiPM and that of analog electronics. Further, external control determines rap rate for SiPM bias voltage. Consequently, the external control protects analog electronics from damage.

There is no conventional technique known that incorporates high voltage SiPM and low voltage circuitry on a sequence.

It would be desirable to have an efficient technique to incorporate high voltage power on sequence and voltage ramp control on the SiPM.

BRIEF DESCRIPTION OF THE DRAWING

Figure 1 depicts inclusion of electronic circuitry on the SiPM to form hybrid SiPM.

DETAILED DESCRIPTION

The present invention includes a technique for incorporating high voltage power on sequence and voltage ramp control on a silicon photomultiplier (SiPM). The technique includes electronic circuitry on the SiPM to form a hybrid SiPM. The electronic circuitry includes high voltage complementary metal oxide semiconductor (CMOS) wells and lower voltage control logic and/or amplifiers. A high voltage gate is placed in line with SiPM cathode voltage.  The high voltage gate is controlled by a low voltage power provided by low voltage electronic circuitry. When th...